+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
# The board has separate JTAG ports for cpu and CPLD/FPGA devices
# Chaining is done on IO interfaces if desired.
# Override this in the interface config for parallel dongles
reset_config trst_and_srst separate
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
+# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
# 29LV650 64Mbit Flash
-flash bank cfi 0x00000000 0x800000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME