tcl/stm32u5x: fix clock config used at 'reset init'

[fw/openocd] / tcl / board / avnet_ultrazed-eg.cfg

diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index a0ac5c6a743b21bbea77c96263b00d69dcb22eb2..3e4a11a3e45a1911fc514446763489b42541142d 100644 (file)
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -1,6 +1,6 @@
 #
 # AVNET UltraZED EG StarterKit
-# UlraScale-EG plus IO Carrier with on-board digilent smt2
+# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
 #
 source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
 # jtag transport only
@@ -9,8 +9,8 @@ transport select jtag
 reset_config none
 
 # slow default clock
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME uscale
 
-source [find target/xilinx_ultrascale.cfg]
+source [find target/xilinx_zynqmp.cfg]