;# set master_pll_div 1
;# set master_pll_mul 13
- set val [expr $::AT91_WDT_WDV] ;# Counter Value
- set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
- set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
+ set val $::AT91_WDT_WDV ;# Counter Value
+ set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
+ set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
;# SDRAMC_CR - Configuration register
- set val [expr $::AT91_SDRAMC_NC_9]
+ set val $::AT91_SDRAMC_NC_9
set val [expr {$val | $::AT91_SDRAMC_NR_13}]
set val [expr {$val | $::AT91_SDRAMC_NB_4}]
set val [expr {$val | $::AT91_SDRAMC_CAS_3}]