* src/z80/gen.c (genFunction, genEndFunction): fixed bug 1160666,

[fw/sdcc] / src / z80 / peeph-z80.def

diff --git a/src/z80/peeph-z80.def b/src/z80/peeph-z80.def
index 90336ddebac53678c64eb8e2e62ddb88fe80d46b..948531d9b19fbd006dddd7359bd306a08ccedf71 100644 (file)
--- a/src/z80/peeph-z80.def
+++ b/src/z80/peeph-z80.def
@@ -3,7 +3,128 @@ replace restart {
        bit     %3,a
        jp      %4,%5
 } by {
-        ; Rule 100: Removed redundent load
        bit     %3,%1(%2)
        jp      %4,%5
 }
+replace {
+       ld      %1,%2
+       ld      a,%2
+} by {
+       ld      %1,%2
+       ld      a,%1
+}
+replace {
+       ld      %1,a
+       xor     a,a
+       or      a,%1
+       jp      z,%2
+} by {
+       ld      %1,a
+       or      a,a
+       jp      z,%2
+}
+replace {
+       rlca
+       ld      a,#0x00
+       rla
+} by {
+       rlca
+       and     a,#0x01
+}
+replace {
+       ld      %3,a
+       ld      l,%1
+       ld      h,%2
+       ld      l,(hl)
+       ld      a,%3
+} by {
+       ld      %3,a
+       ld      l,%1
+       ld      h,%2
+       ld      l,(hl)
+} if notVolatile %3
+
+;
+;--------------------------
+;
+replace restart {
+       pop     %1
+       push    %1
+       ld      %1,%2
+} by {
+       ;       z80 removed redundant pop/push
+       ld      %1,%2
+}
+
+replace restart {
+       ld      l,a
+       ld      c,%1
+       ld      a,l
+} by {
+       ld      l,a
+       ld      c,%1
+}
+
+replace restart {
+       ld      c,l
+       ld      a,c
+       and     a,#%1
+       ld      c,a
+       or      a,a
+} by {
+       ;       z80 stream lining 'and' logic
+       ld      a,#%1
+       and     a,l
+       ld      c,a
+}
+
+replace restart {
+       ld      a,c
+       and     a,#%1
+       ld      c,a
+       or      a,a
+} by {
+       ;       z80 stream lining 'and' logic
+       ld      a,#%1
+       and     a,c
+       ld      c,a
+}
+
+replace restart {
+       ld      a,c
+       or      a,#%1
+       ld      c,a
+} by {
+       ;       z80 stream lining 'or' logic
+       ld      a,#%1
+       or      a,c
+       ld      c,a
+}
+
+
+replace {
+%1:
+       in0     a,(%2)
+       and     a,#%3
+       jp      z,%4
+%5:
+       jp      %6
+%4:
+       call    %7
+       jp      %1
+%6:
+       ret
+} by {
+%1:
+       in0     a,(%2)
+       and     a,#%3
+       jp      nz,%5
+%4:
+       call    %7
+       jp      %1
+%5:
+%6:
+       ret
+}
+
+