ARM720 uses the new inheritance/nesting scheme

[fw/openocd] / src / target / xscale.h

diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6cfe76e65b2131a8cb24e1ee5321dd7b4cf7dfda..56db1815083bce7635e81a67c51222ec908530e7 100644 (file)
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -29,18 +29,13 @@
 
 #define        XSCALE_COMMON_MAGIC 0x58534341
 
-typedef struct xscale_jtag_s
-{
-       /* position in JTAG scan chain */
-       jtag_tap_t *tap;
-
-       /* IR length and instructions */
-       int ir_length;
-       uint32_t dbgrx;
-       uint32_t dbgtx;
-       uint32_t ldic;
-       uint32_t dcsr;
-} xscale_jtag_t;
+/* These four JTAG instructions are architecturally defined.
+ * Lengths are core-specific; originally 5 bits, later 7.
+ */
+#define XSCALE_DBGRX   0x02
+#define XSCALE_DBGTX   0x10
+#define XSCALE_LDIC    0x07
+#define XSCALE_SELDCSR 0x09
 
 enum xscale_debug_reason
 {
@@ -90,14 +85,7 @@ typedef struct xscale_common_s
        /* XScale registers (CP15, DBG) */
        reg_cache_t *reg_cache;
 
-       /* pxa250, pxa255, pxa27x, ixp42x, ... */
-       char *variant;
-
-       xscale_jtag_t jtag_info;
-
        /* current state of the debug handler */
-       int handler_installed;
-       int handler_running;
        uint32_t handler_address;
 
        /* target-endian buffers with exception vectors */
@@ -140,12 +128,16 @@ typedef struct xscale_common_s
        armv4_5_mmu_common_t armv4_5_mmu;
        uint32_t cp15_control_reg;
 
-       /* possible future enhancements that go beyond XScale common stuff */
-       void *arch_info;
-
        int fast_memory_access;
 } xscale_common_t;
 
+static inline struct xscale_common_s *
+target_to_xscale(struct target_s *target)
+{
+       return container_of(target->arch_info, struct xscale_common_s,
+                       armv4_5_common);
+}
+
 typedef struct xscale_reg_s
 {
        int dbg_handler_number;