ARM: disassemble two more v6+ instructions

[fw/openocd] / src / target / xscale.c

diff --git a/src/target/xscale.c b/src/target/xscale.c
index f52965a34fc64d75690f37fcd15bca3283897290..d5b1d636b63ee713871fc531705b734232fb84d8 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -857,7 +857,7 @@ static int xscale_arch_state(struct target *target)
                "", "\n(processor reset)", "\n(trace buffer full)"
        };
 
-       if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+       if (armv4_5->common_magic != ARM_COMMON_MAGIC)
        {
                LOG_ERROR("BUG: called for a non-ARMv4/5 target");
                return ERROR_INVALID_ARGUMENTS;
@@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s"
                        "%s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
                         arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->cpsr->value, 0, 32),
@@ -1429,7 +1429,7 @@ static int xscale_step_inner(struct target *target, int current,
 static int xscale_step(struct target *target, int current,
                uint32_t address, int handle_breakpoints)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
        struct breakpoint *breakpoint = target->breakpoints;
 
        uint32_t current_pc;
@@ -1658,7 +1658,7 @@ static int xscale_deassert_reset(struct target *target)
 }
 
 static int xscale_read_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode)
+               int num, enum arm_mode mode)
 {
        /** \todo add debug handler support for core register reads */
        LOG_ERROR("not implemented");
@@ -1666,7 +1666,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int xscale_write_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode, uint32_t value)
+               int num, enum arm_mode mode, uint32_t value)
 {
        /** \todo add debug handler support for core register writes */
        LOG_ERROR("not implemented");
@@ -1675,7 +1675,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
 
 static int xscale_full_context(struct target *target)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
 
        uint32_t *buffer;
 
@@ -1697,11 +1697,11 @@ static int xscale_full_context(struct target *target)
         */
        for (i = 1; i < 7; i++)
        {
-               enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+               enum arm_mode mode = armv4_5_number_to_mode(i);
                bool valid = true;
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are invalid registers in the current mode
@@ -1724,7 +1724,7 @@ static int xscale_full_context(struct target *target)
                /* get banked registers:  r8 to r14; and SPSR
                 * except in USR/SYS mode
                 */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        /* SPSR */
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
@@ -1757,7 +1757,7 @@ static int xscale_full_context(struct target *target)
 
 static int xscale_restore_banked(struct target *target)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
 
        int i, j;
 
@@ -1774,10 +1774,10 @@ static int xscale_restore_banked(struct target *target)
         */
        for (i = 1; i < 7; i++)
        {
-               enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+               enum arm_mode mode = armv4_5_number_to_mode(i);
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are dirty registers in this mode */
@@ -1789,7 +1789,7 @@ static int xscale_restore_banked(struct target *target)
                }
 
                /* if not USR/SYS, check if the SPSR needs to be written */
-               if (mode != ARMV4_5_MODE_SYS)
+               if (mode != ARM_MODE_SYS)
                {
                        if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16).dirty)
@@ -1817,7 +1817,7 @@ dirty:
                }
 
                /* send spsr if not in USR/SYS mode */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
                        xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
@@ -2859,7 +2859,7 @@ static void xscale_build_reg_cache(struct target *target)
        int i;
        int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
 
-       (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+       (*cache_p) = arm_build_reg_cache(target, armv4_5);
 
        (*cache_p)->next = malloc(sizeof(struct reg_cache));
        cache_p = &(*cache_p)->next;