#include <stdlib.h>
#include <string.h>
-#include <sys/types.h>
#include <unistd.h>
#include <errno.h>
return ERROR_OK;
}
-int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
+int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
+ if (tap==NULL)
+ return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- field.out_mask = NULL;
- field.in_value = NULL;
- jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
- jtag_add_ir_scan(1, &field, -1);
+ u8 tmp[4];
+ field.in_value = tmp;
+
+ jtag_add_ir_scan(1, &field, TAP_INVALID);
+
+ jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
free(field.out_value);
}
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_PD);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ jtag_add_end_state(TAP_DRPAUSE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
+ u8 tmp;
+ fields[0].in_value = &tmp;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
+
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ u8 tmp2;
+ fields[2].in_value = &tmp2;
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
+
+ jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- enum tap_state path[3];
+ tap_state_t path[3];
scan_field_t fields[3];
u8 *field0 = malloc(num_words * 1);
int i;
- path[0] = TAP_SDS;
- path[1] = TAP_CD;
- path[2] = TAP_SD;
+ path[0] = TAP_DRSELECT;
+ path[1] = TAP_DRCAPTURE;
+ path[2] = TAP_DRSHIFT;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
+ u8 tmp2;
+ fields[0].in_value = &tmp2;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
+ u8 tmp[4];
+ fields[1].in_value = tmp;
+
-
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ u8 tmp3;
+ fields[2].in_value = &tmp3;
- jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
- jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
+ jtag_add_end_state(TAP_IDLE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
+ jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts=0;
for (i = words_done; i < num_words; i++)
{
fields[0].in_value = &field0[i];
- fields[1].in_handler = buf_to_u32_handler;
- fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path);
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan_now(3, fields, TAP_IDLE);
+
+ jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
+
+ field1[i]=buf_get_u32(tmp, 0, 32);
+
words_scheduled++;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- enum tap_state path[3];
- enum tap_state noconsume_path[6];
+ tap_state_t path[3];
+ tap_state_t noconsume_path[6];
int retval;
struct timeval timeout, now;
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
- path[0] = TAP_SDS;
- path[1] = TAP_CD;
- path[2] = TAP_SD;
+ path[0] = TAP_DRSELECT;
+ path[1] = TAP_DRCAPTURE;
+ path[2] = TAP_DRSHIFT;
- noconsume_path[0] = TAP_SDS;
- noconsume_path[1] = TAP_CD;
- noconsume_path[2] = TAP_E1D;
- noconsume_path[3] = TAP_PD;
- noconsume_path[4] = TAP_E2D;
- noconsume_path[5] = TAP_SD;
+ noconsume_path[0] = TAP_DRSELECT;
+ noconsume_path[1] = TAP_DRCAPTURE;
+ noconsume_path[2] = TAP_DREXIT1;
+ noconsume_path[3] = TAP_DRPAUSE;
+ noconsume_path[4] = TAP_DREXIT2;
+ noconsume_path[5] = TAP_DRSHIFT;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
+
-
-
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ u8 tmp;
+ fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
}
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
+
+ jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
- fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
+
-
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ u8 tmp;
+ fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
LOG_DEBUG("polling RX");
for (;;)
{
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
+
+ jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
/* set rx_valid */
field2 = 0x1;
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
int done_count = 0;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
bits[0]=3;
t[0]=0;
LOG_ERROR("BUG: size neither 4, 2 nor 1");
exit(-1);
}
- jtag_add_dr_out(xscale->jtag_info.chain_pos,
+ jtag_add_dr_out(xscale->jtag_info.tap,
3,
bits,
t,
- TAP_RTI);
+ TAP_IDLE);
buffer += size;
}
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
- jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ jtag_add_end_state(TAP_IDLE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
+ u8 tmp;
+ fields[0].in_value = &tmp;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
+
-
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ u8 tmp2;
+ fields[2].in_value = &tmp2;
+
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
- jtag_add_dr_scan(3, fields, -1);
+ jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
- jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ jtag_add_end_state(TAP_IDLE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
if (mini)
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[0].out_mask = NULL;
+
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+
+
+
+
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- fields[1].out_mask = NULL;
+
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- jtag_add_dr_scan(2, fields, -1);
+
+
+
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
fields[0].num_bits = 32;
fields[0].out_value = packet;
for (word = 0; word < 8; word++)
{
buf_set_u32(packet, 0, 32, buffer[word]);
- cmd = parity(*((u32*)packet));
- jtag_add_dr_scan(2, fields, -1);
+
+ u32 value;
+ memcpy(&value, packet, sizeof(u32));
+ cmd = parity(value);
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
}
jtag_execute_queue();
scan_field_t fields[2];
- jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ jtag_add_end_state(TAP_IDLE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[0].out_mask = NULL;
+
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+
+
+
+
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- fields[1].out_mask = NULL;
+
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- jtag_add_dr_scan(2, fields, -1);
+
+
+
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- u32 current_pc, next_pc;
+ u32 next_pc;
int retval;
int i;
-
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
- u32 current_opcode;
+ u32 current_opcode, current_pc;
+ current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
- jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ jtag_add_end_state(TAP_IDLE);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
jtag_execute_queue();
/* assert reset */
if (target->reset_halt)
{
- int retval;
+ int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
u32 binary_size;
u32 buf_cnt;
- int i;
+ u32 i;
int retval;
breakpoint_t *breakpoint = target->breakpoints;
/* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000);
- jtag_add_runtest(2030, TAP_RTI);
+ jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */
for (; buf_cnt < 32; buf_cnt += 4)
{
- cache_line[buf_cnt / 4] = 0xe1a08008;
+ cache_line[buf_cnt / 4] = 0xe1a08008;
}
/* only load addresses other than the reset vectors */
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
- jtag_add_runtest(30, TAP_RTI);
+ jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000);
jtag_add_reset(0, 0);
}
-
return ERROR_OK;
}
int xscale_soft_reset_halt(struct target_s *target)
{
-
return ERROR_OK;
}
int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
{
-
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
u32 *buf32;
- int i;
+ u32 i;
int retval;
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
}
return ERROR_OK;
-
}
int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
LOG_INFO("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- else
- {
- xscale->ibcr_available--;
- }
if ((breakpoint->length != 2) && (breakpoint->length != 4))
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
+ if (breakpoint->type == BKPT_HARD)
+ {
+ xscale->ibcr_available--;
+ }
+
return ERROR_OK;
}
(((instruction.type == ARM_B) ||
(instruction.type == ARM_BL) ||
(instruction.type == ARM_BLX)) &&
- (instruction.info.b_bl_bx_blx.target_address != -1)))
+ (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)))
{
xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
}
int xscale_quit(void)
{
-
return ERROR_OK;
}
-int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, const char *variant)
+int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
u32 high_reset_branch, low_reset_branch;
xscale->variant = strdup(variant);
/* prepare JTAG information for the new target */
- xscale->jtag_info.chain_pos = chain_pos;
+ xscale->jtag_info.tap = tap;
xscale->jtag_info.dbgrx = 0x02;
xscale->jtag_info.dbgtx = 0x10;
{
xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
- xscale_init_arch_info(target, xscale, target->chain_position, target->variant);
+ xscale_init_arch_info(target, xscale, target->tap, target->variant);
xscale_build_reg_cache(target);
return ERROR_OK;
int domain;
u32 ap;
-
if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
{
return retval;
return ERROR_OK;
}
-
int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
- command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+ command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
return ERROR_OK;
}
register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
- register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
+ register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
projects / fw / openocd / blobdiff