* Copyright (C) 2006, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008 Øyvind Harboe *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
{
- if (tap==NULL)
+ if (tap == NULL)
return ERROR_FAIL;
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
- jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
+ jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
static void xscale_getbuf(jtag_callback_data_t arg)
{
- uint8_t *in=(uint8_t *)arg;
- *((uint32_t *)in)=buf_get_u32(in, 0, 32);
+ uint8_t *in = (uint8_t *)arg;
+ *((uint32_t *)in) = buf_get_u32(in, 0, 32);
}
int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
{
- if (num_words==0)
+ if (num_words == 0)
return ERROR_INVALID_ARGUMENTS;
- int retval=ERROR_OK;
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
- int attempts=0;
+ int attempts = 0;
while (words_done < num_words)
{
/* schedule reads */
jtag_add_pathmove(3, path);
- fields[1].in_value = (uint8_t *)(field1+i);
+ fields[1].in_value = (uint8_t *)(field1 + i);
jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
- jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1+i));
+ jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
words_scheduled++;
}
int j;
for (j = i; j < num_words - 1; j++)
{
- field0[j] = field0[j+1];
- field1[j] = field1[j+1];
+ field0[j] = field0[j + 1];
+ field1[j] = field1[j + 1];
}
words_scheduled--;
}
}
- if (words_scheduled==0)
+ if (words_scheduled == 0)
{
if (attempts++==1000)
{
LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
- retval=ERROR_TARGET_TIMEOUT;
+ retval = ERROR_TARGET_TIMEOUT;
break;
}
}
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
- jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
- jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
+ jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
{
goto done;
}
- if (debug_level>=3)
+ if (debug_level >= 3)
{
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
{
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
- jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
- jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
+ jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
}
if (!(field0_in & 1))
goto done;
- if (debug_level>=3)
+ if (debug_level >= 3)
{
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
- jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
+ jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
+ jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
}
else
{
- retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
+ retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
else
{
- retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
+ retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
int xscale_poll(target_t *target)
{
- int retval=ERROR_OK;
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
return retval;
/* get r0, pc, r1 to r7 and cpsr */
- if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
+ if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
return retval;
/* move r0 from buffer to register cache */
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
}
}
- if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK)
+ if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
return retval;
return ERROR_OK;
reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
- if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK)
+ if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
return retval;
return ERROR_OK;
}
/* update vector tables */
- if ((retval=xscale_update_vectors(target))!=ERROR_OK)
+ if ((retval = xscale_update_vectors(target)) != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
}
LOG_DEBUG("enable single-step");
- if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK)
+ if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
return retval;
/* restore banked registers */
- if ((retval=xscale_restore_context(target))!=ERROR_OK)
+ if ((retval = xscale_restore_context(target)) != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.buffer_enabled)
{
- if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
return retval;
- if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
return retval;
}
else
- if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
return retval;
/* send CPSR */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
- if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK)
+ if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
return retval;
/* wait for and process debug entry */
- if ((retval=xscale_debug_entry(target))!=ERROR_OK)
+ if ((retval = xscale_debug_entry(target)) != ERROR_OK)
return retval;
LOG_DEBUG("disable single-step");
- if ((retval=xscale_disable_single_step(target))!=ERROR_OK)
+ if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
- if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK)
+ if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
- if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK)
+ if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
return retval;
}
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ target_state_name(target));
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
* we can't enter User mode on an XScale (unpredictable),
* but User shares registers with SYS
*/
- for(i = 1; i < 7; i++)
+ for (i = 1; i < 7; i++)
{
int valid = 1;
* we can't enter User mode on an XScale (unpredictable),
* but User shares registers with SYS
*/
- for(i = 1; i < 7; i++)
+ for (i = 1; i < 7; i++)
{
int dirty = 0;
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words */
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
- if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
+ if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words to be written*/
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
}
}
#endif
- if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
+ if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- uint8_t enable=0;
+ uint8_t enable = 0;
reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
- register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
+ register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
projects / fw / openocd / blobdiff