Change tap_state naming to be consistent with SVF documentation.

[fw/openocd] / src / target / xscale.c

diff --git a/src/target/xscale.c b/src/target/xscale.c
index ef476027ae982088ee361fbd073aff9820bfc414..304477656f49b3c71bd000a6af9a9cd3da361512 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -252,7 +252,7 @@ int xscale_read_dcsr(target_t *target)
        u8 field2_check_value = 0x0;
        u8 field2_check_mask = 0x1;
 
-       jtag_add_end_state(TAP_PD);
+       jtag_add_end_state(TAP_DRPAUSE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
 
        buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@@ -300,7 +300,7 @@ int xscale_read_dcsr(target_t *target)
        fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
        fields[1].in_value = NULL;
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
 
        jtag_add_dr_scan(3, fields, -1);
 
@@ -332,9 +332,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
 
        int i;
 
-       path[0] = TAP_SDS;
-       path[1] = TAP_CD;
-       path[2] = TAP_SD;
+       path[0] = TAP_DRSELECT;
+       path[1] = TAP_DRCAPTURE;
+       path[2] = TAP_DRSHIFT;
 
        fields[0].tap = xscale->jtag_info.tap;
        fields[0].num_bits = 3;
@@ -362,9 +362,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
        fields[2].in_value = NULL;
        jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
-       jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
+       jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 
        /* repeat until all words have been collected */
        int attempts=0;
@@ -379,7 +379,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
                        fields[1].in_handler_priv = (u8*)&field1[i];
 
                        jtag_add_pathmove(3, path);
-                       jtag_add_dr_scan(3, fields, TAP_RTI);
+                       jtag_add_dr_scan(3, fields, TAP_IDLE);
                        words_scheduled++;
                }
 
@@ -442,20 +442,20 @@ int xscale_read_tx(target_t *target, int consume)
        u8 field2_check_value = 0x0;
        u8 field2_check_mask = 0x1;
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
 
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
 
-       path[0] = TAP_SDS;
-       path[1] = TAP_CD;
-       path[2] = TAP_SD;
+       path[0] = TAP_DRSELECT;
+       path[1] = TAP_DRCAPTURE;
+       path[2] = TAP_DRSHIFT;
 
-       noconsume_path[0] = TAP_SDS;
-       noconsume_path[1] = TAP_CD;
-       noconsume_path[2] = TAP_E1D;
-       noconsume_path[3] = TAP_PD;
-       noconsume_path[4] = TAP_E2D;
-       noconsume_path[5] = TAP_SD;
+       noconsume_path[0] = TAP_DRSELECT;
+       noconsume_path[1] = TAP_DRCAPTURE;
+       noconsume_path[2] = TAP_DREXIT1;
+       noconsume_path[3] = TAP_DRPAUSE;
+       noconsume_path[4] = TAP_DREXIT2;
+       noconsume_path[5] = TAP_DRSHIFT;
 
        fields[0].tap = xscale->jtag_info.tap;
        fields[0].num_bits = 3;
@@ -499,7 +499,7 @@ int xscale_read_tx(target_t *target, int consume)
                        jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
                }
 
-               jtag_add_dr_scan(3, fields, TAP_RTI);
+               jtag_add_dr_scan(3, fields, TAP_IDLE);
 
                if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
@@ -551,7 +551,7 @@ int xscale_write_rx(target_t *target)
        u8 field2_check_value = 0x0;
        u8 field2_check_mask = 0x1;
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
 
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
 
@@ -588,7 +588,7 @@ int xscale_write_rx(target_t *target)
        LOG_DEBUG("polling RX");
        for (;;)
        {
-               jtag_add_dr_scan(3, fields, TAP_RTI);
+               jtag_add_dr_scan(3, fields, TAP_IDLE);
 
                if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
@@ -617,7 +617,7 @@ int xscale_write_rx(target_t *target)
 
        /* set rx_valid */
        field2 = 0x1;
-       jtag_add_dr_scan(3, fields, TAP_RTI);
+       jtag_add_dr_scan(3, fields, TAP_IDLE);
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
@@ -640,7 +640,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
 
        int done_count = 0;
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
 
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
 
@@ -683,7 +683,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
                                3,
                                bits,
                                t,
-                               TAP_RTI);
+                               TAP_IDLE);
                buffer += size;
        }
 
@@ -726,7 +726,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
        if (ext_dbg_brk != -1)
                xscale->external_debug_break = ext_dbg_brk;
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
 
        buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@@ -796,7 +796,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
 
        LOG_DEBUG("loading miniIC at 0x%8.8x", va);
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
 
        /* CMD is b010 for Main IC and b011 for Mini IC */
@@ -859,7 +859,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
 
        scan_field_t fields[2];
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
 
        /* CMD for invalidate IC line b000, bits [6:4] b000 */
@@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target)
        /* select DCSR instruction (set endstate to R-T-I to ensure we don't
         * end up in T-L-R, which would reset JTAG
         */
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
 
        /* set Hold reset, Halt mode and Trap Reset */
@@ -1620,7 +1620,7 @@ int xscale_assert_reset(target_t *target)
 
     if (target->reset_halt)
     {
-       int retval;
+       int retval;
                if ((retval = target_halt(target))!=ERROR_OK)
                        return retval;
     }
@@ -1671,7 +1671,7 @@ int xscale_deassert_reset(target_t *target)
                /* wait 300ms; 150 and 100ms were not enough */
                jtag_add_sleep(300*1000);
 
-               jtag_add_runtest(2030, TAP_RTI);
+               jtag_add_runtest(2030, TAP_IDLE);
                jtag_execute_queue();
 
                /* set Hold reset, Halt mode and Trap Reset */
@@ -1734,7 +1734,7 @@ int xscale_deassert_reset(target_t *target)
                xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
                xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
 
-               jtag_add_runtest(30, TAP_RTI);
+               jtag_add_runtest(30, TAP_IDLE);
 
                jtag_add_sleep(100000);
 
@@ -3381,7 +3381,7 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **
                command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
 
        if (dcache)
-               command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+               command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
 
        return ERROR_OK;
 }