RTOS Thread awareness support wip

[fw/openocd] / src / target / target.h

diff --git a/src/target/target.h b/src/target/target.h
index 2bf96689fdfa2326264bfc43c129749f0ec38b86..5b67bf345daa2e3e5e28cee98599de8003ba87cb 100644 (file)
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -8,6 +8,9 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
+ *   Copyright (C) 2011 by Broadcom Corporation                            *
+ *   Evan Hunter - ehunter@broadcom.com                                    *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -84,7 +87,7 @@ enum target_debug_reason
        DBG_REASON_UNDEFINED = 6
 };
 
-enum target_endianess
+enum target_endianness
 {
        TARGET_ENDIAN_UNKNOWN = 0,
        TARGET_BIG_ENDIAN = 1, TARGET_LITTLE_ENDIAN = 2
@@ -139,7 +142,7 @@ struct target
        uint32_t backup_working_area;                   /* whether the content of the working area has to be preserved */
        struct working_area *working_areas;/* list of allocated working areas */
        enum target_debug_reason debug_reason;/* reason why the target entered debug state */
-       enum target_endianess endianness;       /* target endianess */
+       enum target_endianness endianness;      /* target endianness */
        // also see: target_state_name()
        enum target_state state;                        /* the current backend-state (running, halted, ...) */
        struct reg_cache *reg_cache;            /* the first register cache of the target (core regs) */
@@ -155,6 +158,14 @@ struct target
                                                                                 * lots of halted/resumed info when stepping in debugger. */
        bool halt_issued;                                       /* did we transition to halted state? */
        long long halt_issued_time;                     /* Note time when halt was issued */
+
+       bool dbgbase_set;                                       /* By default the debug base is not set */
+       uint32_t dbgbase;                                       /* Really a Cortex-A specific option, but there is no
+                                                                                  system in place to support target specific options
+                                                                                  currently. */
+       struct rtos *rtos;                                      /* Instance of Real Time Operating System support */
+       bool rtos_auto_detect;                          /* A flag that indicates that the RTOS has been specified as "auto" 
+                                            * and must be detected when symbols are offered */
 };
 
 /** Returns the instance-specific name of the specified target. */
@@ -403,7 +414,7 @@ int target_read_memory(struct target *target,
  * This routine is wrapper for target->type->write_memory.
  */
 int target_write_memory(struct target *target,
-               uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+               uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
 
 /**
  * Write @a count items of 4 bytes to the memory of @a target at
@@ -413,7 +424,7 @@ int target_write_memory(struct target *target,
  * This routine is wrapper for target->type->bulk_write_memory.
  */
 int target_bulk_write_memory(struct target *target,
-               uint32_t address, uint32_t count, uint8_t *buffer);
+               uint32_t address, uint32_t count, const uint8_t *buffer);
 
 /*
  * Write to target memory using the virtual address.
@@ -440,7 +451,7 @@ int target_bulk_write_memory(struct target *target,
  * peripheral registers which do not support byte operations.
  */
 int target_write_buffer(struct target *target,
-               uint32_t address, uint32_t size, uint8_t *buffer);
+               uint32_t address, uint32_t size, const uint8_t *buffer);
 int target_read_buffer(struct target *target,
                uint32_t address, uint32_t size, uint8_t *buffer);
 int target_checksum_memory(struct target *target,