target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / startup.tcl

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 976cd2af5edacdf84748e63e4f91200fe4618d4b..ca39b1816111914ebc2ffe9f399c744fbafa8fdb 100644 (file)
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -119,7 +119,7 @@ proc ocd_process_reset_inner { MODE } {
                                continue
                        }
 
-                       # Wait upto 1 second for target to halt.  Why 1sec? Cause
+                       # Wait up to 1 second for target to halt. Why 1sec? Cause
                        # the JTAG tap reset signal might be hooked to a slow
                        # resistor/capacitor circuit - and it might take a while
                        # to charge
@@ -205,7 +205,7 @@ proc init_target_events {} {
        foreach t $targets {
                set_default_target_event $t gdb-flash-erase-start "reset init"
                set_default_target_event $t gdb-flash-write-end "reset halt"
-               set_default_target_event $t gdb-attach "halt"
+               set_default_target_event $t gdb-attach "halt 1000"
        }
 }