+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2013 Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
uint32_t max_level = nds32->max_interrupt_level;
uint32_t cur_level = nds32->current_interrupt_level;
- if ((1 <= cur_level) && (cur_level < max_level)) {
- if (IR0 == reg_no) {
+ if ((cur_level >= 1) && (cur_level < max_level)) {
+ if (reg_no == IR0) {
LOG_DEBUG("Map PSW to IPSW");
return IR1;
- } else if (PC == reg_no) {
+ } else if (reg_no == PC) {
LOG_DEBUG("Map PC to IPC");
return IR9;
}
- } else if ((2 <= cur_level) && (cur_level < max_level)) {
- if (R26 == reg_no) {
+ } else if ((cur_level >= 2) && (cur_level < max_level)) {
+ if (reg_no == R26) {
LOG_DEBUG("Mapping P0 to P_P0");
return IR12;
- } else if (R27 == reg_no) {
+ } else if (reg_no == R27) {
LOG_DEBUG("Mapping P1 to P_P1");
return IR13;
- } else if (IR1 == reg_no) {
+ } else if (reg_no == IR1) {
LOG_DEBUG("Mapping IPSW to P_IPSW");
return IR2;
- } else if (IR4 == reg_no) {
+ } else if (reg_no == IR4) {
LOG_DEBUG("Mapping EVA to P_EVA");
return IR5;
- } else if (IR6 == reg_no) {
+ } else if (reg_no == IR6) {
LOG_DEBUG("Mapping ITYPE to P_ITYPE");
return IR7;
- } else if (IR9 == reg_no) {
+ } else if (reg_no == IR9) {
LOG_DEBUG("Mapping IPC to P_IPC");
return IR10;
}
} else if (cur_level == max_level) {
- if (PC == reg_no) {
+ if (reg_no == PC) {
LOG_DEBUG("Mapping PC to O_IPC");
return IR11;
}
/* enable breakpoint (physical address) */
aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
- LOG_DEBUG("Add hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
+ LOG_DEBUG("Add hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
bp->address);
hbr_index++;
else
return ERROR_FAIL;
- LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
+ LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
bp->address);
hbr_index++;
/* set value */
aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
- LOG_DEBUG("Add hardware wathcpoint %" PRId32 " at %08" PRIx32 " mask %08" PRIx32, wp_num,
+ LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32, wp_num,
wp->address, wp->mask);
}
/* disable watchpoint */
aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
- LOG_DEBUG("Remove hardware wathcpoint %" PRId32 " at %08" PRIx32 " mask %08" PRIx32,
+ LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32,
wp_num, wp->address, wp->mask);
}
aice_write_register(aice, IR2, val_ir2);
}
- /* get origianl DT bit and set to current state let debugger has same memory view
+ /* get original DT bit and set to current state let debugger has same memory view
PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */
aice_read_register(aice, IR1, &val_ir1);
modified_psw = val_ir0 | (val_ir1 & 0x80);
if (enable_watchpoint)
CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
- if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
+ if (nds32_examine_debug_reason(nds32) != ERROR_OK) {
nds32->target->state = backup_state;
/* re-activate all hardware breakpoints & watchpoints */
}
static int nds32_v2_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum)
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
LOG_WARNING("Not implemented: %s", __func__);
return ERROR_OK;
} else if (breakpoint->type == BKPT_SOFT) {
result = nds32_add_software_breakpoint(target, breakpoint);
- if (ERROR_OK != result) {
+ if (result != ERROR_OK) {
/* auto convert to hardware breakpoint if failed */
if (nds32->auto_convert_hw_bp) {
/* convert to hardware breakpoint */
struct mem_param *mem_params,
int num_reg_params,
struct reg_param *reg_params,
- uint32_t entry_point,
- uint32_t exit_point,
+ target_addr_t entry_point,
+ target_addr_t exit_point,
int timeout_ms,
void *arch_info)
{
return ERROR_OK;
}
-static int nds32_v2_translate_address(struct target *target, uint32_t *address)
+static int nds32_v2_translate_address(struct target *target, target_addr_t *address)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- uint32_t physical_address;
+ target_addr_t physical_address;
/* Following conditions need to do address translation
* 1. BUS mode
* 2. CPU mode under maximum interrupt level */
- if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
- ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_BUS) ||
+ ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
nds32_reach_max_interrupt_level(nds32))) {
- if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
+ if (target->type->virt2phys(target, *address, &physical_address) == ERROR_OK)
*address = physical_address;
else
return ERROR_FAIL;
return ERROR_OK;
}
-static int nds32_v2_read_buffer(struct target *target, uint32_t address,
+static int nds32_v2_read_buffer(struct target *target, target_addr_t address,
uint32_t size, uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_read_buffer(target, address, size, buffer);
}
-static int nds32_v2_write_buffer(struct target *target, uint32_t address,
+static int nds32_v2_write_buffer(struct target *target, target_addr_t address,
uint32_t size, const uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_write_buffer(target, address, size, buffer);
}
-static int nds32_v2_read_memory(struct target *target, uint32_t address,
+static int nds32_v2_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_read_memory(target, address, size, count, buffer);
}
-static int nds32_v2_write_memory(struct target *target, uint32_t address,
+static int nds32_v2_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
projects / fw / openocd / blobdiff