+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2013 Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
uint32_t max_level = nds32->max_interrupt_level;
uint32_t cur_level = nds32->current_interrupt_level;
- if ((1 <= cur_level) && (cur_level < max_level)) {
- if (IR0 == reg_no) {
+ if ((cur_level >= 1) && (cur_level < max_level)) {
+ if (reg_no == IR0) {
LOG_DEBUG("Map PSW to IPSW");
return IR1;
- } else if (PC == reg_no) {
+ } else if (reg_no == PC) {
LOG_DEBUG("Map PC to IPC");
return IR9;
}
- } else if ((2 <= cur_level) && (cur_level < max_level)) {
- if (R26 == reg_no) {
+ } else if ((cur_level >= 2) && (cur_level < max_level)) {
+ if (reg_no == R26) {
LOG_DEBUG("Mapping P0 to P_P0");
return IR12;
- } else if (R27 == reg_no) {
+ } else if (reg_no == R27) {
LOG_DEBUG("Mapping P1 to P_P1");
return IR13;
- } else if (IR1 == reg_no) {
+ } else if (reg_no == IR1) {
LOG_DEBUG("Mapping IPSW to P_IPSW");
return IR2;
- } else if (IR4 == reg_no) {
+ } else if (reg_no == IR4) {
LOG_DEBUG("Mapping EVA to P_EVA");
return IR5;
- } else if (IR6 == reg_no) {
+ } else if (reg_no == IR6) {
LOG_DEBUG("Mapping ITYPE to P_ITYPE");
return IR7;
- } else if (IR9 == reg_no) {
+ } else if (reg_no == IR9) {
LOG_DEBUG("Mapping IPC to P_IPC");
return IR10;
}
} else if (cur_level == max_level) {
- if (PC == reg_no) {
+ if (reg_no == PC) {
LOG_DEBUG("Mapping PC to O_IPC");
return IR11;
}
/* enable breakpoint (physical address) */
aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
- LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
+ LOG_DEBUG("Add hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
bp->address);
hbr_index++;
else
return ERROR_FAIL;
- LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
+ LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
bp->address);
hbr_index++;
/* set value */
aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
- LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
+ LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32, wp_num,
wp->address, wp->mask);
}
/* disable watchpoint */
aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
- LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
+ LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32,
wp_num, wp->address, wp->mask);
}
nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
if (nds32_reach_max_interrupt_level(nds32)) {
- LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
+ LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->",
nds32->current_interrupt_level);
/* decrease interrupt level */
return ERROR_OK;
}
-
/* There is a case that single step also trigger another interrupt,
then HSS bit in psw(ir0) will push to ipsw(ir1).
Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
aice_write_register(aice, IR2, val_ir2);
}
- /* get origianl DT bit and set to current state let debugger has same memory view
+ /* get original DT bit and set to current state let debugger has same memory view
PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */
aice_read_register(aice, IR1, &val_ir1);
modified_psw = val_ir0 | (val_ir1 & 0x80);
{
LOG_DEBUG("nds32_v2_debug_entry");
- jtag_poll_set_enabled(false);
-
if (nds32->virtual_hosting)
LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
"under V1/V2 architecture. -->");
- struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
-
- CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
-
- if (enable_watchpoint)
- CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
-
+ enum target_state backup_state = nds32->target->state;
nds32->target->state = TARGET_HALTED;
- nds32_examine_debug_reason(nds32);
if (nds32->init_arch_info_after_halted == false) {
/* init architecture info according to config registers */
/* REVISIT entire cache should already be invalid !!! */
register_cache_invalidate(nds32->core_cache);
+ /* deactivate all hardware breakpoints */
+ CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
+
+ if (enable_watchpoint)
+ CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
+
+ if (nds32_examine_debug_reason(nds32) != ERROR_OK) {
+ nds32->target->state = backup_state;
+
+ /* re-activate all hardware breakpoints & watchpoints */
+ CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
+
+ if (enable_watchpoint) {
+ /* activate all watchpoints */
+ CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
+ }
+
+ return ERROR_FAIL;
+ }
+
/* check interrupt level before .full_context(), because
- * get_mapped_reg needs current_interrupt_level information */
+ * get_mapped_reg() in nds32_full_context() needs current_interrupt_level
+ * information */
+ struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
nds32_v2_check_interrupt_stack(nds32_v2);
/* Save registers. */
*/
static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
{
- struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
+ LOG_DEBUG("nds32_v2_leave_debug_state");
+
+ struct target *target = nds32->target;
/* activate all hardware breakpoints */
CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
}
/* restore interrupt stack */
+ struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
nds32_v2_restore_interrupt_stack(nds32_v2);
/* restore PSW, PC, and R0 ... after flushing any modified
* registers.
*/
- CHECK_RETVAL(nds32_restore_context(nds32->target));
+ CHECK_RETVAL(nds32_restore_context(target));
register_cache_invalidate(nds32->core_cache);
- jtag_poll_set_enabled(true);
-
- return ERROR_OK;
-}
-
-static int nds32_v2_soft_reset_halt(struct target *target)
-{
- /* TODO: test it */
- struct nds32 *nds32 = target_to_nds32(target);
- struct aice_port_s *aice = target_to_aice(target);
-
- aice_assert_srst(aice, AICE_SRST);
-
- /* halt core and set pc to 0x0 */
- int retval = target_halt(target);
- if (retval != ERROR_OK)
- return retval;
-
- /* start fetching from IVB */
- uint32_t value_ir3;
- nds32_get_mapped_reg(nds32, IR3, &value_ir3);
- nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
-
return ERROR_OK;
}
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
- /* call target_poll() to avoid "Halt timed out" */
- CHECK_RETVAL(target_poll(target));
- } else {
- jtag_poll_set_enabled(false);
}
return ERROR_OK;
}
static int nds32_v2_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum)
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
LOG_WARNING("Not implemented: %s", __func__);
LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
"breakpoints/watchpoints! The limit of "
"combined hardware breakpoints/watchpoints "
- "is %d. -->", nds32_v2->n_hbr);
+ "is %" PRId32 ". -->", nds32_v2->n_hbr);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
return ERROR_OK;
} else if (breakpoint->type == BKPT_SOFT) {
result = nds32_add_software_breakpoint(target, breakpoint);
- if (ERROR_OK != result) {
+ if (result != ERROR_OK) {
/* auto convert to hardware breakpoint if failed */
if (nds32->auto_convert_hw_bp) {
/* convert to hardware breakpoint */
if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
"breakpoints/watchpoints! The limit of "
- "combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
+ "combined hardware breakpoints/watchpoints is %" PRId32 ". -->", nds32_v2->n_hbr);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
return ERROR_OK;
}
+/**
+ * find out which watchpoint hits
+ * get exception address and compare the address to watchpoints
+ */
+static int nds32_v2_hit_watchpoint(struct target *target,
+ struct watchpoint **hit_watchpoint)
+{
+ uint32_t exception_address;
+ struct watchpoint *wp;
+ static struct watchpoint scan_all_watchpoint;
+ struct nds32 *nds32 = target_to_nds32(target);
+
+ scan_all_watchpoint.address = 0;
+ scan_all_watchpoint.rw = WPT_WRITE;
+ scan_all_watchpoint.next = 0;
+ scan_all_watchpoint.unique_id = 0x5CA8;
+
+ exception_address = nds32->watched_address;
+
+ if (exception_address == 0) {
+ /* send watch:0 to tell GDB to do software scan for hitting multiple watchpoints */
+ *hit_watchpoint = &scan_all_watchpoint;
+ return ERROR_OK;
+ }
+
+ for (wp = target->watchpoints; wp; wp = wp->next) {
+ if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
+ /* TODO: dispel false match */
+ *hit_watchpoint = wp;
+ return ERROR_OK;
+ }
+ }
+
+ return ERROR_FAIL;
+}
+
static int nds32_v2_run_algorithm(struct target *target,
int num_mem_params,
struct mem_param *mem_params,
int num_reg_params,
struct reg_param *reg_params,
- uint32_t entry_point,
- uint32_t exit_point,
+ target_addr_t entry_point,
+ target_addr_t exit_point,
int timeout_ms,
void *arch_info)
{
nds32_v2->next_hbr_index = 0;
- LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
+ LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target),
nds32_v2->n_hbr);
nds32->target->state = TARGET_RUNNING;
return ERROR_OK;
}
-static int nds32_v2_translate_address(struct target *target, uint32_t *address)
+static int nds32_v2_translate_address(struct target *target, target_addr_t *address)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- uint32_t physical_address;
+ target_addr_t physical_address;
/* Following conditions need to do address translation
* 1. BUS mode
* 2. CPU mode under maximum interrupt level */
- if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
- ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_BUS) ||
+ ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
nds32_reach_max_interrupt_level(nds32))) {
- if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
+ if (target->type->virt2phys(target, *address, &physical_address) == ERROR_OK)
*address = physical_address;
else
return ERROR_FAIL;
return ERROR_OK;
}
-static int nds32_v2_read_buffer(struct target *target, uint32_t address,
+static int nds32_v2_read_buffer(struct target *target, target_addr_t address,
uint32_t size, uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_read_buffer(target, address, size, buffer);
}
-static int nds32_v2_write_buffer(struct target *target, uint32_t address,
+static int nds32_v2_write_buffer(struct target *target, target_addr_t address,
uint32_t size, const uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_write_buffer(target, address, size, buffer);
}
-static int nds32_v2_read_memory(struct target *target, uint32_t address,
+static int nds32_v2_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
return nds32_read_memory(target, address, size, count, buffer);
}
-static int nds32_v2_write_memory(struct target *target, uint32_t address,
+static int nds32_v2_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct nds32 *nds32 = target_to_nds32(target);
struct nds32_memory *memory = &(nds32->memory);
- if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+ if ((memory->access_channel == NDS_MEMORY_ACC_CPU) &&
(target->state != TARGET_HALTED)) {
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
.assert_reset = nds32_assert_reset,
.deassert_reset = nds32_v2_deassert_reset,
- .soft_reset_halt = nds32_v2_soft_reset_halt,
/* register access */
.get_gdb_reg_list = nds32_get_gdb_reg_list,
.remove_breakpoint = nds32_v2_remove_breakpoint,
.add_watchpoint = nds32_v2_add_watchpoint,
.remove_watchpoint = nds32_v2_remove_watchpoint,
+ .hit_watchpoint = nds32_v2_hit_watchpoint,
/* MMU */
.mmu = nds32_mmu,
projects / fw / openocd / blobdiff