flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / src / target / nds32.h

diff --git a/src/target/nds32.h b/src/target/nds32.h
index eddfe7a052494e46128b9b1dd318db9d88232a11..d0b680a97c6546cab70b4df6f1e265795d8f209b 100644 (file)
--- a/src/target/nds32.h
+++ b/src/target/nds32.h
@@ -1,25 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
-#ifndef __NDS32_H__
-#define __NDS32_H__
+#ifndef OPENOCD_TARGET_NDS32_H
+#define OPENOCD_TARGET_NDS32_H
 
 #include <jtag/jtag.h>
 #include "target.h"
@@ -84,7 +71,7 @@ enum nds32_syscall_id {
        NDS32_SYSCALL_ERRNO = 6001,
 };
 
-#define NDS32_COMMON_MAGIC (int)0xADE5ADE5
+#define NDS32_COMMON_MAGIC 0xADE5ADE5U
 
 struct nds32_edm {
 
@@ -219,7 +206,7 @@ struct nds32_misc_config {
        bool div_instruction;
        bool mac_instruction;
        int audio_isa;
-       bool L2_cache;
+       bool l2_cache;
        bool reduce_register;
        bool addr_24;
        bool interruption_level;
@@ -237,7 +224,8 @@ struct nds32_misc_config {
  * Represents a generic Andes core.
  */
 struct nds32 {
-       int common_magic;
+       unsigned int common_magic;
+
        struct reg_cache *core_cache;
 
        /** Handle for the debug module. */
@@ -362,8 +350,7 @@ struct nds32 {
 
 struct nds32_reg {
        int32_t num;
-       uint32_t value;
-       uint64_t value_64;
+       uint8_t value[8];
        struct target *target;
        struct nds32 *nds32;
        bool enable;
@@ -403,23 +390,23 @@ extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *
 extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
 
 extern int nds32_edm_config(struct nds32 *nds32);
-extern int nds32_cache_sync(struct target *target, uint32_t address, uint32_t length);
+extern int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length);
 extern int nds32_mmu(struct target *target, int *enabled);
-extern int nds32_virtual_to_physical(struct target *target, uint32_t address,
-               uint32_t *physical);
-extern int nds32_read_phys_memory(struct target *target, uint32_t address,
+extern int nds32_virtual_to_physical(struct target *target, target_addr_t address,
+               target_addr_t *physical);
+extern int nds32_read_phys_memory(struct target *target, target_addr_t address,
                uint32_t size, uint32_t count, uint8_t *buffer);
-extern int nds32_write_phys_memory(struct target *target, uint32_t address,
+extern int nds32_write_phys_memory(struct target *target, target_addr_t address,
                uint32_t size, uint32_t count, const uint8_t *buffer);
 extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
 extern int nds32_examine_debug_reason(struct nds32 *nds32);
 extern int nds32_step(struct target *target, int current,
-               uint32_t address, int handle_breakpoints);
+               target_addr_t address, int handle_breakpoints);
 extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
 extern int nds32_halt(struct target *target);
 extern int nds32_poll(struct target *target);
 extern int nds32_resume(struct target *target, int current,
-               uint32_t address, int handle_breakpoints, int debug_execution);
+               target_addr_t address, int handle_breakpoints, int debug_execution);
 extern int nds32_assert_reset(struct target *target);
 extern int nds32_init(struct nds32 *nds32);
 extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
@@ -434,27 +421,27 @@ extern int nds32_profiling(struct target *target, uint32_t *samples,
 /** Convert target handle to generic Andes target state handle. */
 static inline struct nds32 *target_to_nds32(struct target *target)
 {
-       assert(target != NULL);
+       assert(target);
        return target->arch_info;
 }
 
 /** */
 static inline struct aice_port_s *target_to_aice(struct target *target)
 {
-       assert(target != NULL);
+       assert(target);
        return target->tap->priv;
 }
 
 static inline bool is_nds32(struct nds32 *nds32)
 {
-       assert(nds32 != NULL);
+       assert(nds32);
        return nds32->common_magic == NDS32_COMMON_MAGIC;
 }
 
 static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
 {
-       assert(nds32 != NULL);
+       assert(nds32);
        return nds32->max_interrupt_level == nds32->current_interrupt_level;
 }
 
-#endif /* __NDS32_H__ */
+#endif /* OPENOCD_TARGET_NDS32_H */