* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
}
if (reg->valid) {
+ uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
LOG_DEBUG("reading register(cached) %" PRIi32 "(%s), value: 0x%8.8" PRIx32,
- reg_arch_info->num, reg->name, reg_arch_info->value);
+ reg_arch_info->num, reg->name, val);
return ERROR_OK;
}
int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num);
if (reg_arch_info->enable == false) {
- reg_arch_info->value = NDS32_REGISTER_DISABLE;
+ buf_set_u32(reg_arch_info->value, 0, 32, NDS32_REGISTER_DISABLE);
retval = ERROR_FAIL;
} else {
- if ((nds32->fpu_enable == false) &&
- (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) {
- reg_arch_info->value = 0;
+ uint32_t val = 0;
+ if ((nds32->fpu_enable == false)
+ && (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) {
retval = ERROR_OK;
- } else if ((nds32->audio_enable == false) &&
- (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) {
- reg_arch_info->value = 0;
+ } else if ((nds32->audio_enable == false)
+ && (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) {
retval = ERROR_OK;
} else {
- retval = aice_read_register(aice,
- mapped_regnum, &(reg_arch_info->value));
+ retval = aice_read_register(aice, mapped_regnum, &val);
}
+ buf_set_u32(reg_arch_info->value, 0, 32, val);
LOG_DEBUG("reading register %" PRIi32 "(%s), value: 0x%8.8" PRIx32,
- reg_arch_info->num, reg->name, reg_arch_info->value);
+ reg_arch_info->num, reg->name, val);
}
if (retval == ERROR_OK) {
return ERROR_OK;
if (reg_arch_info->enable == false) {
- reg_arch_info->value_64 = NDS32_REGISTER_DISABLE;
+ buf_set_u64(reg_arch_info->value, 0, 64, NDS32_REGISTER_DISABLE);
retval = ERROR_FAIL;
} else {
- if ((nds32->fpu_enable == false) &&
- ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) {
- reg_arch_info->value_64 = 0;
+ uint64_t val = 0;
+ if ((nds32->fpu_enable == false)
+ && ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) {
retval = ERROR_OK;
} else {
- retval = aice_read_reg_64(aice, reg_arch_info->num,
- &(reg_arch_info->value_64));
+ retval = aice_read_reg_64(aice, reg_arch_info->num, &val);
}
+ buf_set_u64(reg_arch_info->value, 0, 64, val);
}
if (retval == ERROR_OK) {
buf_set_u32(reg->value, 0, 32, 0);
} else {
buf_set_u32(reg->value, 0, 32, value);
- aice_write_register(aice, mapped_regnum, reg_arch_info->value);
+ uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
+ aice_write_register(aice, mapped_regnum, val);
/* After set value to registers, read the value from target
* to avoid W1C inconsistency. */
- aice_read_register(aice, mapped_regnum, &(reg_arch_info->value));
+ aice_read_register(aice, mapped_regnum, &val);
+ buf_set_u32(reg_arch_info->value, 0, 32, val);
}
reg->valid = true;
reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1);
if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) {
- reg_list[i].value = &(reg_arch_info[i].value_64);
+ reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &nds32_reg_access_type_64;
reg_list[i].reg_data_type->type = REG_TYPE_IEEE_DOUBLE;
reg_list[i].reg_data_type->id = "ieee_double";
reg_list[i].group = "float";
} else {
- reg_list[i].value = &(reg_arch_info[i].value);
+ reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &nds32_reg_access_type;
reg_list[i].group = "general";
return aice_read_mem_unit(aice, address, size, count, buffer);
}
-int nds32_read_phys_memory(struct target *target, uint32_t address,
+int nds32_read_phys_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct aice_port_s *aice = target_to_aice(target);
return aice_write_mem_unit(aice, address, size, count, buffer);
}
-int nds32_write_phys_memory(struct target *target, uint32_t address,
+int nds32_write_phys_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct aice_port_s *aice = target_to_aice(target);
i, buf_get_u32(reg->value, 0, 32));
reg_arch_info = reg->arch_info;
- if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31)
- aice_write_reg_64(aice, reg_arch_info->num, reg_arch_info->value_64);
- else
- aice_write_register(aice, reg_arch_info->num, reg_arch_info->value);
+ if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) {
+ uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64);
+ aice_write_reg_64(aice, reg_arch_info->num, val);
+ } else {
+ uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
+ aice_write_register(aice, reg_arch_info->num, val);
+ }
+
reg->valid = true;
reg->dirty = false;
}
return ERROR_OK;
}
-int nds32_virtual_to_physical(struct target *target, uint32_t address, uint32_t *physical)
+int nds32_virtual_to_physical(struct target *target, target_addr_t address, target_addr_t *physical)
{
struct nds32 *nds32 = target_to_nds32(target);
return ERROR_FAIL;
}
-int nds32_cache_sync(struct target *target, uint32_t address, uint32_t length)
+int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length)
{
struct aice_port_s *aice = target_to_aice(target);
struct nds32 *nds32 = target_to_nds32(target);
/* Because PSW.IT is turned off under debug exception, address MUST
* be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
* address translation or not. */
- uint32_t physical_addr;
+ target_addr_t physical_addr;
if (ERROR_FAIL == target->type->virt2phys(target, cur_address,
&physical_addr))
return ERROR_FAIL;
}
int nds32_step(struct target *target, int current,
- uint32_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
address = nds32_nextpc(nds32, current, address);
- LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
/** set DSSIM */
uint32_t ir14_value;
}
int nds32_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+ target_addr_t address, int handle_breakpoints, int debug_execution)
{
- LOG_DEBUG("current %d address %08" PRIx32
+ LOG_DEBUG("current %d address %08" TARGET_PRIxADDR
" handle_breakpoints %d"
" debug_execution %d",
current, address, handle_breakpoints, debug_execution);
address = nds32_nextpc(nds32, current, address);
- LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
if (!debug_execution)
target_free_all_working_areas(target);
struct aice_port_s *aice = target_to_aice(target);
struct nds32_cpu_version *cpu_version = &(nds32->cpu_version);
+ /* TODO: apply hw reset signal in not examined state */
+ if (!(target_was_examined(target))) {
+ LOG_WARNING("Reset is not asserted because the target is not examined.");
+ LOG_WARNING("Use a reset button or power cycle the target.");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
if (target->reset_halt) {
if ((nds32->soft_reset_halt)
|| (nds32->edm.version < 0x51)
projects / fw / openocd / blobdiff