#include "mips32.h"
#include "mips_m4k.h"
#include "mips32_dmaacc.h"
-#include "jtag.h"
-#include "log.h"
+#include "target_type.h"
-#include <stdlib.h>
-#include <string.h>
/* cli handling */
int mips_m4k_poll(target_t *target);
int mips_m4k_halt(struct target_s *target);
int mips_m4k_soft_reset_halt(struct target_s *target);
-int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
-int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
+int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int mips_m4k_quit(void);
int mips_m4k_examine(struct target_s *target);
int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
+int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum);
target_type_t mips_m4k_target =
{
.read_memory = mips_m4k_read_memory,
.write_memory = mips_m4k_write_memory,
.bulk_write_memory = mips_m4k_bulk_write_memory,
- .checksum_memory = NULL,
+ .checksum_memory = mips_m4k_checksum_memory,
.blank_check_memory = NULL,
.run_algorithm = mips32_run_algorithm,
int mips_m4k_examine_debug_reason(target_t *target)
{
- int break_status;
+ uint32_t break_status;
int retval;
if ((target->debug_reason != DBG_REASON_DBGRQ)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
- u32 debug_reg;
+ uint32_t debug_reg;
/* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg);
mips32_save_context(target);
LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
- *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
+ *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
return ERROR_OK;
int retval;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
- u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
target->state = TARGET_HALTED;
if (target->state == TARGET_RESET)
{
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
+ if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
{
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
- mips_m4k_common_t *mips_m4k = mips32->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
if (target->reset_halt)
{
/* use hardware to catch reset */
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
}
else
{
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
- if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
+ if (strcmp(target->variant, "ejtag_srst") == 0)
{
- u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
+ /* disable interrupts while stepping */
+ mips32_enable_interrupts(target, 0);
+
/* exit debug mode */
- mips_ejtag_exit_debug(ejtag_info, 1);
+ mips_ejtag_exit_debug(ejtag_info);
mips_m4k_debug_entry(target);
return ERROR_OK;
}
-int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL;
- u32 resume_pc;
+ uint32_t resume_pc;
if (target->state != TARGET_HALTED)
{
}
}
- /* exit debug mode - enable interrupts if required */
- mips_ejtag_exit_debug(ejtag_info, !debug_execution);
+ /* enable interrupts if we are running */
+ mips32_enable_interrupts(target, !debug_execution);
+
+ /* exit debug mode */
+ mips_ejtag_exit_debug(ejtag_info);
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
return ERROR_OK;
}
-int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ /* disable interrupts while stepping */
+ mips32_enable_interrupts(target, 0);
+
/* exit debug mode */
- mips_ejtag_exit_debug(ejtag_info, 1);
+ mips_ejtag_exit_debug(ejtag_info);
/* registers are now invalid */
mips32_invalidate_core_regs(target);
{
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list;
-
+ int retval;
+
if (breakpoint->set)
{
LOG_WARNING("breakpoint already set");
}
else if (breakpoint->type == BKPT_SOFT)
{
-
+ if (breakpoint->length == 4)
+ {
+ uint32_t verify = 0xffffffff;
+
+ if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (verify != MIPS32_SDBBP)
+ {
+ LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
+ }
+ else
+ {
+ uint16_t verify = 0xffff;
+
+ if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (verify != MIPS16_SDBBP)
+ {
+ LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
+ }
+
+ breakpoint->set = 20; /* Any nice value but 0 */
}
return ERROR_OK;
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list;
-
+ int retval;
+
if (!breakpoint->set)
{
LOG_WARNING("breakpoint not set");
}
else
{
-
+ /* restore original instruction (kept in target endianness) */
+ if (breakpoint->length == 4)
+ {
+ uint32_t current_instr;
+
+ /* check that user program has not modified breakpoint instruction */
+ if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (current_instr == MIPS32_SDBBP)
+ {
+ if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
+ else
+ {
+ uint16_t current_instr;
+
+ /* check that user program has not modified breakpoint instruction */
+ if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (current_instr == MIPS16_SDBBP)
+ {
+ if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
}
breakpoint->set = 0;
{
mips32_common_t *mips32 = target->arch_info;
- if (mips32->num_inst_bpoints_avail < 1)
+ if (breakpoint->type == BKPT_HARD)
{
- LOG_INFO("no hardware breakpoint available");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- /* default to hardware for now */
- breakpoint->type = BKPT_HARD;
+ if (mips32->num_inst_bpoints_avail < 1)
+ {
+ LOG_INFO("no hardware breakpoint available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ mips32->num_inst_bpoints_avail--;
+ }
- mips32->num_inst_bpoints_avail--;
mips_m4k_set_breakpoint(target, breakpoint);
return ERROR_OK;
}
}
-int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- switch (size)
- {
- case 4:
- case 2:
- case 1:
- /* if noDMA off, use DMAACC mode for memory read */
- if(ejtag_info->impcode & EJTAG_IMP_NODMA)
- return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
- else
- return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
+ /* if noDMA off, use DMAACC mode for memory read */
+ int retval;
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
+ retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+ else
+ retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+ if (ERROR_OK != retval)
+ return retval;
+
+ /* TAP data register is loaded LSB first (little endian) */
+ if (target->endianness == TARGET_BIG_ENDIAN)
+ {
+ uint32_t i, t32;
+ uint16_t t16;
+
+ for(i = 0; i < (count*size); i += size)
+ {
+ switch(size)
+ {
+ case 4:
+ t32 = le_to_h_u32(&buffer[i]);
+ h_u32_to_be(&buffer[i], t32);
+ break;
+ case 2:
+ t16 = le_to_h_u16(&buffer[i]);
+ h_u16_to_be(&buffer[i], t16);
+ break;
+ }
+ }
}
return ERROR_OK;
}
-int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- switch (size)
- {
- case 4:
- case 2:
- case 1:
- /* if noDMA off, use DMAACC mode for memory write */
- if(ejtag_info->impcode & EJTAG_IMP_NODMA)
- mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
- else
- mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
- break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
- }
+ /* TAP data register is loaded LSB first (little endian) */
+ if (target->endianness == TARGET_BIG_ENDIAN)
+ {
+ uint32_t i, t32;
+ uint16_t t16;
- return ERROR_OK;
+ for(i = 0; i < (count*size); i += size)
+ {
+ switch(size)
+ {
+ case 4:
+ t32 = be_to_h_u32(&buffer[i]);
+ h_u32_to_le(&buffer[i], t32);
+ break;
+ case 2:
+ t16 = be_to_h_u16(&buffer[i]);
+ h_u16_to_le(&buffer[i], t16);
+ break;
+ }
+ }
+ }
+
+ /* if noDMA off, use DMAACC mode for memory write */
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
+ return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+ else
+ return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
}
int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
return ERROR_OK;
}
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
- if (variant)
- {
- mips_m4k->variant = strdup(variant);
- }
- else
- {
- mips_m4k->variant = strdup("");
- }
-
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
/* initialize mips4k specific info */
- mips32_init_arch_info(target, mips32, tap, variant);
+ mips32_init_arch_info(target, mips32, tap);
mips32->arch_info = mips_m4k;
return ERROR_OK;
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
- mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
+ mips_m4k_init_arch_info(target, mips_m4k, target->tap);
return ERROR_OK;
}
int retval;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
- u32 idcode = 0;
+ uint32_t idcode = 0;
- if (!target->type->examined)
+ if (!target_was_examined(target))
{
- mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
-
+ mips_ejtag_get_idcode(ejtag_info, &idcode);
+ ejtag_info->idcode = idcode;
+
if (((idcode >> 1) & 0x7FF) == 0x29)
{
/* we are using a pic32mx so select ejtag port
return ERROR_OK;
}
-int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
+int mips_m4k_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
return mips_m4k_write_memory(target, address, 4, count, buffer);
}
+
+int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum)
+{
+ return ERROR_FAIL; /* use bulk read method */
+}
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