target/adi_v5_swd: add support for SWD multidrop

[fw/openocd] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d1d094520ab753bf970bfed9a1b4328a4fd2e451..ca4416981029932b2dd1b9d0a0e9360791bbdd64 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -131,7 +131,7 @@ static struct target *get_mips_m4k(struct target *target, int32_t coreid)
        struct target *curr;
 
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                curr = head->target;
                if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
                        return curr;
@@ -146,7 +146,7 @@ static int mips_m4k_halt_smp(struct target *target)
        struct target_list *head;
        struct target *curr;
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                int ret = ERROR_OK;
                curr = head->target;
                if ((curr != target) && (curr->state != TARGET_HALTED))
@@ -186,7 +186,7 @@ static int mips_m4k_poll(struct target *target)
        /*  the next polling trigger an halt event sent to gdb */
        if ((target->state == TARGET_HALTED) && (target->smp) &&
                (target->gdb_service) &&
-               (target->gdb_service->target == NULL)) {
+               (!target->gdb_service->target)) {
                target->gdb_service->target =
                        get_mips_m4k(target, target->gdb_service->core[1]);
                target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -417,7 +417,7 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
        struct target *curr;
 
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                int ret = ERROR_OK;
                curr = head->target;
                if ((curr != target) && (curr->state != TARGET_RUNNING)) {
@@ -880,8 +880,8 @@ static int mips_m4k_set_watchpoint(struct target *target,
         * and exclude both load and store accesses from  watchpoint
         * condition evaluation
        */
-       int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
-                       (0xff << EJTAG_DBCn_BLM_SHIFT);
+       int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
+                       (0xff << EJTAG_DBCN_BLM_SHIFT);
 
        if (watchpoint->set) {
                LOG_WARNING("watchpoint already set");
@@ -907,13 +907,13 @@ static int mips_m4k_set_watchpoint(struct target *target,
 
        switch (watchpoint->rw) {
                case WPT_READ:
-                       enable &= ~EJTAG_DBCn_NOLB;
+                       enable &= ~EJTAG_DBCN_NOLB;
                        break;
                case WPT_WRITE:
-                       enable &= ~EJTAG_DBCn_NOSB;
+                       enable &= ~EJTAG_DBCN_NOSB;
                        break;
                case WPT_ACCESS:
-                       enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
+                       enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
                        break;
                default:
                        LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
@@ -1045,7 +1045,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
 
        if (size > 1) {
                t = malloc(count * size * sizeof(uint8_t));
-               if (t == NULL) {
+               if (!t) {
                        LOG_ERROR("Out of memory");
                        return ERROR_FAIL;
                }
@@ -1061,7 +1061,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
 
        /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
        /* endianness, but byte array should represent target endianness       */
-       if (ERROR_OK == retval) {
+       if (retval == ERROR_OK) {
                switch (size) {
                case 4:
                        target_buffer_set_u32_array(target, buffer, count, t);
@@ -1072,7 +1072,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
                }
        }
 
-       if ((size > 1) && (t != NULL))
+       if (size > 1)
                free(t);
 
        return retval;
@@ -1112,7 +1112,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
                /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
                /* endianness, but byte array represents target endianness               */
                t = malloc(count * size * sizeof(uint8_t));
-               if (t == NULL) {
+               if (!t) {
                        LOG_ERROR("Out of memory");
                        return ERROR_FAIL;
                }
@@ -1135,10 +1135,9 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
        else
                retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
 
-       if (t != NULL)
-               free(t);
+       free(t);
 
-       if (ERROR_OK != retval)
+       if (retval != ERROR_OK)
                return retval;
 
        return ERROR_OK;
@@ -1219,7 +1218,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
        if (address & 0x3u)
                return ERROR_TARGET_UNALIGNED_ACCESS;
 
-       if (mips32->fast_data_area == NULL) {
+       if (!mips32->fast_data_area) {
                /* Get memory for block write handler
                 * we preserve this area between calls and gain a speed increase
                 * of about 3kb/sec when writing flash
@@ -1251,7 +1250,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
        /* but byte array represents target endianness                      */
        uint32_t *t = NULL;
        t = malloc(count * sizeof(uint32_t));
-       if (t == NULL) {
+       if (!t) {
                LOG_ERROR("Out of memory");
                return ERROR_FAIL;
        }
@@ -1261,8 +1260,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
        retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
                        count, t);
 
-       if (t != NULL)
-               free(t);
+       free(t);
 
        if (retval != ERROR_OK)
                LOG_ERROR("Fastdata access Failed");
@@ -1309,11 +1307,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
                        retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
                        if (retval != ERROR_OK) {
                                command_print(CMD,
-                                               "couldn't access reg %" PRIi32,
+                                               "couldn't access reg %" PRIu32,
                                                cp0_reg);
                                return ERROR_OK;
                        }
-                       command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+                       command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
                                        cp0_reg, cp0_sel, value);
 
                } else if (CMD_ARGC == 3) {
@@ -1322,11 +1320,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
                        retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
                        if (retval != ERROR_OK) {
                                command_print(CMD,
-                                               "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+                                               "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
                                                cp0_reg,  cp0_sel);
                                return ERROR_OK;
                        }
-                       command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+                       command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
                                        cp0_reg, cp0_sel, value);
                }
        }