int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int mips_m4k_quit(void);
int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
int mips_m4k_examine(struct target_s *target);
.target_create = mips_m4k_target_create,
.init_target = mips_m4k_init_target,
.examine = mips_m4k_examine,
- .quit = mips_m4k_quit
};
int mips_m4k_examine_debug_reason(target_t *target)
int mips_m4k_debug_entry(target_t *target)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t debug_reg;
/* read debug register */
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
return ERROR_OK;
}
int mips_m4k_poll(target_t *target)
{
int retval;
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
int mips_m4k_halt(struct target_s *target)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
int mips_m4k_assert_reset(target_t *target)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
int mips_m4k_single_step_core(target_t *target)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL;
uint32_t resume_pc;
int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL;
if (target->state != TARGET_HALTED)
int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- mips32_common_t *mips32 = target->arch_info;
- mips32_comparator_t * comparator_list = mips32->inst_break_list;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips32_comparator * comparator_list = mips32->inst_break_list;
int retval;
if (breakpoint->set)
target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
- LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
+ LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
}
int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
/* get pointers to arch-specific information */
- mips32_common_t *mips32 = target->arch_info;
- mips32_comparator_t * comparator_list = mips32->inst_break_list;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips32_comparator * comparator_list = mips32->inst_break_list;
int retval;
if (!breakpoint->set)
comparator_list[bp_num].used = 0;
comparator_list[bp_num].bp_value = 0;
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
-
+
}
else
{
int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- mips32_common_t *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target->arch_info;
if (breakpoint->type == BKPT_HARD)
{
int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
/* get pointers to arch-specific information */
- mips32_common_t *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target->arch_info;
if (target->state != TARGET_HALTED)
{
return ERROR_OK;
}
-int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int mips_m4k_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- mips32_common_t *mips32 = target->arch_info;
- mips32_comparator_t * comparator_list = mips32->data_break_list;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips32_comparator * comparator_list = mips32->data_break_list;
int wp_num = 0;
/*
* watchpoint enabled, ignore all byte lanes in value register
* and exclude both load and store accesses from watchpoint
* condition evaluation
*/
- int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
+ int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
(0xff << EJTAG_DBCn_BLM_SHIFT);
-
+
if (watchpoint->set)
{
LOG_WARNING("watchpoint already set");
target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
-
+
return ERROR_OK;
}
-int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int mips_m4k_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
- mips32_common_t *mips32 = target->arch_info;
- mips32_comparator_t * comparator_list = mips32->data_break_list;
-
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips32_comparator * comparator_list = mips32->data_break_list;
+
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
return ERROR_OK;
}
-int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int mips_m4k_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- mips32_common_t *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target->arch_info;
if (mips32->num_data_bpoints_avail < 1)
{
LOG_INFO("no hardware watchpoints available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
mips32->num_data_bpoints_avail--;
mips_m4k_set_watchpoint(target, watchpoint);
return ERROR_OK;
}
-int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int mips_m4k_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
- mips32_common_t *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target->arch_info;
if (target->state != TARGET_HALTED)
{
void mips_m4k_enable_watchpoints(struct target_s *target)
{
- watchpoint_t *watchpoint = target->watchpoints;
+ struct watchpoint *watchpoint = target->watchpoints;
/* set any pending watchpoints */
while (watchpoint)
int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
if (ERROR_OK != retval)
return retval;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = le_to_h_u32(&buffer[i]);
- h_u32_to_be(&buffer[i], t32);
- break;
- case 2:
- t16 = le_to_h_u16(&buffer[i]);
- h_u16_to_be(&buffer[i], t16);
- break;
- }
- }
- }
-
return ERROR_OK;
}
int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = be_to_h_u32(&buffer[i]);
- h_u32_to_le(&buffer[i], t32);
- break;
- case 2:
- t16 = be_to_h_u16(&buffer[i]);
- h_u16_to_le(&buffer[i], t16);
- break;
- }
- }
- }
-
/* if noDMA off, use DMAACC mode for memory write */
if (ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
return ERROR_OK;
}
-int mips_m4k_quit(void)
-{
- return ERROR_OK;
-}
-
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, struct jtag_tap *tap)
{
- mips32_common_t *mips32 = &mips_m4k->mips32_common;
+ struct mips32_common *mips32 = &mips_m4k->mips32_common;
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
int mips_m4k_examine(struct target_s *target)
{
int retval;
- mips32_common_t *mips32 = target->arch_info;
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t idcode = 0;
if (!target_was_examined(target))
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