arm7_9_execute_sys_speed error propagation. Found by code inspection, no observed...

[fw/openocd] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index be7f59ec8c38ab7e2bd334605985f110b59c14a9..0e544df7e00fbeac39cb5a4228b995a9340174ac 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -236,7 +236,7 @@ int mips_m4k_assert_reset(target_t *target)
        mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
        
        LOG_DEBUG("target->state: %s", 
-                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+               Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
        
        if (!(jtag_reset_config & RESET_HAS_SRST))
        {
@@ -256,14 +256,21 @@ int mips_m4k_assert_reset(target_t *target)
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
        }
        
-       /* here we should issue a srst only, but we may have to assert trst as well */
-       if (jtag_reset_config & RESET_SRST_PULLS_TRST)
-       {
-               jtag_add_reset(1, 1);
-       }
-       else
-       {
-               jtag_add_reset(0, 1);
+       if (strcmp(target->variant, "ejtag_srst") == 0) {
+               u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+               LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } else {
+               /* here we should issue a srst only, but we may have to assert trst as well */
+               if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+               {
+                       jtag_add_reset(1, 1);
+               }
+               else
+               {
+                       jtag_add_reset(0, 1);
+               }
        }
        
        target->state = TARGET_RESET;
@@ -271,12 +278,12 @@ int mips_m4k_assert_reset(target_t *target)
 
        mips32_invalidate_core_regs(target);
 
-    if (target->reset_halt)
-    {
-       int retval;
+       if (target->reset_halt)
+       {
+               int retval;
                if ((retval = target_halt(target))!=ERROR_OK)
                        return retval;
-    }
+       }
        
        
        return ERROR_OK;
@@ -285,7 +292,7 @@ int mips_m4k_assert_reset(target_t *target)
 int mips_m4k_deassert_reset(target_t *target)
 {
        LOG_DEBUG("target->state: %s", 
-                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+               Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
        
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -320,7 +327,7 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
        }
        
        /* current = 1: continue on current pc, otherwise continue at <address> */
-       if (!current) 
+       if (!current)
        {
                buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
                mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
@@ -606,7 +613,7 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int c
        /* initialize mips4k specific info */
        mips32_init_arch_info(target, mips32, chain_pos, variant);
        mips32->arch_info = mips_m4k;
-               
+       
        return ERROR_OK;
 }