Added mips_ejtag_drscan_32_out() for optimization.

[fw/openocd] / src / target / mips_ejtag.h

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 93b4a6aef48a52e7df2adaa6277e8b67cef44927..a6ed95a509b5bdc9c287ecbe4ed98ade5ccec42d 100644 (file)
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -40,7 +40,18 @@
 #define EJTAG_INST_TCBDATA             0x12
 #define EJTAG_INST_BYPASS              0xFF
 
-/* debug control register bits ECR */
+/* microchip PIC32MX specific instructions */
+#define MTAP_SW_MTAP                   0x04
+#define MTAP_SW_ETAP                   0x05
+#define MTAP_COMMAND                   0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST                 0xd1
+#define MCHP_DE_ASSERT_RST             0xd0
+#define MCHP_ERASE                             0xfc
+#define MCHP_STATUS                            0x00
+
+/* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF                 (1 << 1)
 #define EJTAG_CTRL_TIF                 (1 << 2)
 #define EJTAG_CTRL_BRKST               (1 << 3)
@@ -87,37 +98,49 @@
 #define EJTAG_DEBUG_DBD                        (1 << 31)
 
 /* implementaion register bits */
+#define EJTAG_IMP_R3K                  (1 << 28)
+#define EJTAG_IMP_DINT                 (1 << 24)
 #define EJTAG_IMP_NODMA                        (1 << 14)
 #define EJTAG_IMP_MIPS16               (1 << 16)
+#define EJTAG_DCR_MIPS64               (1 << 0)
 
-/* breakpoint support */
+/* Debug Control Register DCR */
 #define EJTAG_DCR                              0xFF300000
+#define EJTAG_DCR_ENM                  (1 << 29)
+#define EJTAG_DCR_DB                   (1 << 17)
+#define EJTAG_DCR_IB                   (1 << 16)
+#define EJTAG_DCR_INTE                 (1 << 4)
+
+/* breakpoint support */
 #define EJTAG_IBS                              0xFF301000
 #define EJTAG_IBA1                             0xFF301100
 #define EJTAG_DBS                              0xFF302000
 #define EJTAG_DBA1                             0xFF302100
-#define                EJTAG_DBCn_NOSB                         (1 << 13)
-#define                EJTAG_DBCn_NOLB                         (1 << 12)
-#define                EJTAG_DBCn_BLM_MASK                     0xff
-#define                EJTAG_DBCn_BLM_SHIFT            4
-#define                EJTAG_DBCn_BE                           (1 << 0)
+#define        EJTAG_DBCn_NOSB                 (1 << 13)
+#define        EJTAG_DBCn_NOLB                 (1 << 12)
+#define        EJTAG_DBCn_BLM_MASK             0xff
+#define        EJTAG_DBCn_BLM_SHIFT    4
+#define        EJTAG_DBCn_BE                   (1 << 0)
 
 struct mips_ejtag
 {
        struct jtag_tap *tap;
        uint32_t impcode;
        uint32_t idcode;
-       /*int use_dma;*/
        uint32_t ejtag_ctrl;
+       int fast_access_save;
 };
 
-int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
-               int new_instr, void *delete_me_and_submit_patch);
+void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
+               int new_instr);
 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
-int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
+void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
 
 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);