* *
* Copyright (C) 2008 by David T.L. Wong *
* *
+ * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "mips32.h"
#include "mips_ejtag.h"
-#include "binarybuffer.h"
-#include "log.h"
-#include "jtag.h"
+void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
+{
+ struct jtag_tap *tap;
-#include <stdlib.h>
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
-int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler)
-{
- jtag_device_t *device = jtag_get_device(ejtag_info->chain_pos);
-
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
- {
- scan_field_t field;
- u8 t[4];
-
- field.device = ejtag_info->chain_pos;
- field.num_bits = device->ir_length;
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
+ struct scan_field field;
+ uint8_t t[4];
+
+ field.num_bits = tap->ir_length;
field.out_value = t;
- buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- field.out_mask = NULL;
+ buf_set_u32(t, 0, field.num_bits, new_instr);
field.in_value = NULL;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = handler;
- field.in_handler_priv = NULL;
- jtag_add_ir_scan(1, &field, -1);
+
+ jtag_add_ir_scan(tap, &field, TAP_IDLE);
}
-
- return ERROR_OK;
}
-int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t handler)
+int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
{
- scan_field_t field;
-
- jtag_add_end_state(TAP_RTI);
-
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
-
- field.device = ejtag_info->chain_pos;
+ struct scan_field field;
+ uint8_t r[4];
+
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
+
field.num_bits = 32;
field.out_value = NULL;
- field.out_mask = NULL;
- field.in_value = (void*)idcode;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = NULL;
- field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, -1);
-
- if (jtag_execute_queue() != ERROR_OK)
- {
+ field.in_value = r;
+
+ jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
+
+ int retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
LOG_ERROR("register read failed");
+ return retval;
}
-
+
+ *idcode = buf_get_u32(field.in_value, 0, 32);
+
return ERROR_OK;
}
-int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t handler)
+static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
{
- scan_field_t field;
-
- jtag_add_end_state(TAP_RTI);
-
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
-
- field.device = ejtag_info->chain_pos;
+ struct scan_field field;
+ uint8_t r[4];
+
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
+
field.num_bits = 32;
field.out_value = NULL;
- field.out_mask = NULL;
- field.in_value = (void*)impcode;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = NULL;
- field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, -1);
-
- if (jtag_execute_queue() != ERROR_OK)
- {
+ field.in_value = r;
+
+ jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
+
+ int retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
LOG_ERROR("register read failed");
+ return retval;
}
-
+
+ *impcode = buf_get_u32(field.in_value, 0, 32);
+
return ERROR_OK;
}
-int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
+void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
{
- jtag_device_t *device;
- device = jtag_get_device(ejtag_info->chain_pos);
- scan_field_t field;
- u8 t[4];
+ assert(ejtag_info->tap != NULL);
+ struct jtag_tap *tap = ejtag_info->tap;
+
+ struct scan_field field;
+ uint8_t out_scan[12];
+
+ /* processor access "all" register 96 bit */
+ field.num_bits = 96;
+
+ field.out_value = out_scan;
+ buf_set_u32(out_scan, 0, 32, ctrl);
+ buf_set_u32(out_scan + 4, 0, 32, data);
+ buf_set_u32(out_scan + 8, 0, 32, 0);
+
+ field.in_value = in_scan_buf;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+ keep_alive();
+}
+
+int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
+{
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field field;
+ uint8_t t[4], r[4];
int retval;
-
- field.device = ejtag_info->chain_pos;
+
field.num_bits = 32;
field.out_value = t;
- buf_set_u32(field.out_value, 0, field.num_bits, *data);
- field.out_mask = NULL;
- field.in_value = (u8*)data;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = NULL;
- field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, -1);
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ buf_set_u32(t, 0, field.num_bits, *data);
+ field.in_value = r;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
LOG_ERROR("register read failed");
return retval;
}
-
+
+ *data = buf_get_u32(field.in_value, 0, 32);
+
+ keep_alive();
+
return ERROR_OK;
}
-int mips_ejtag_step_enable(mips_ejtag_t *ejtag_info)
-{
- u32 code[] = {
- MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */
- MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
- MIPS32_ORI(1,1,0x0100), /* set SSt bit in debug reg */
- MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
- MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */
- MIPS32_NOP,
- MIPS32_B(NEG16(7)),
- MIPS32_NOP,
- };
-
- mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
- 0, NULL, 0, NULL, 1);
-
- return ERROR_OK;
+void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
+{
+ uint8_t t[4];
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field field;
+
+ field.num_bits = 32;
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, data);
+
+ field.in_value = NULL;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
}
-int mips_ejtag_step_disable(mips_ejtag_t *ejtag_info)
+
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
{
- u32 code[] = {
- MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
- MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
- MIPS32_SW(1,0,15), /* sw $2,($15) */
- MIPS32_SW(2,0,15), /* sw $3,($15) */
- MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
- MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */
- MIPS32_ORI(2,2,0xFEFF),
- MIPS32_AND(1,1,2),
- MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
- MIPS32_LW(2,0,15),
- MIPS32_LW(1,0,15),
- MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
- MIPS32_NOP,
- MIPS32_B(NEG16(15)),
- MIPS32_NOP,
- };
-
- mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
- 0, NULL, 0, NULL, 1);
-
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field field;
+ uint8_t t[4] = {0, 0, 0, 0}, r[4];
+ int retval;
+
+ field.num_bits = 8;
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, *data);
+ field.in_value = r;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("register read failed");
+ return retval;
+ }
+
+ *data = buf_get_u32(field.in_value, 0, 32);
+
return ERROR_OK;
}
-int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
-{
- if (enable_step)
- return mips_ejtag_step_enable(ejtag_info);
- return mips_ejtag_step_disable(ejtag_info);
+void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
+{
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field field;
+
+ field.num_bits = 8;
+ field.out_value = &data;
+ field.in_value = NULL;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+}
+
+/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
+int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
+{
+ struct pracc_queue_info ctx = {.max_code = 7};
+ pracc_queue_init(&ctx);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
+ if (!enable_step)
+ pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
+
+ pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
+ pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
-int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
+int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
{
- jtag_add_end_state(TAP_RTI);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-
+ uint32_t ejtag_ctrl;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
+
/* set debug break bit */
- ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK;
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-
+ ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+
/* break bit will be cleared by hardware */
- ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
+ if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) {
+ LOG_ERROR("Failed to enter Debug Mode!");
+ return ERROR_FAIL;
+ }
+
return ERROR_OK;
}
-int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts)
+int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
{
- u32 inst;
- inst = MIPS32_DRET;
-
- /* TODO : enable/disable interrrupts */
-
+ uint32_t instr = MIPS32_DRET;
+ struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
+
/* execute our dret instruction */
- mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
-
- return ERROR_OK;
-}
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
-int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
-{
- u32 code[] = {
- MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
- MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
- MIPS32_SW(1,0,15), /* sw $1,($15) */
- MIPS32_SW(2,0,15), /* sw $2,($15) */
- MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */
- MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
- MIPS32_MFC0(2,23,0), /* move COP0 Debug to $1 */
- MIPS32_SW(2,0,1),
- MIPS32_LW(2,0,15),
- MIPS32_LW(1,0,15),
- MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
- MIPS32_NOP,
- MIPS32_B(NEG16(14)),
- MIPS32_NOP,
- };
-
- mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
- 0, NULL, 1, debug_reg, 1);
-
- return ERROR_OK;
+ /* pic32mx workaround, false pending at low core clock */
+ jtag_add_sleep(1000);
+ return ctx.retval;
}
-int mips_ejtag_init(mips_ejtag_t *ejtag_info)
+int mips_ejtag_init(struct mips_ejtag *ejtag_info)
{
- u32 ejtag_version;
-
- mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode, NULL);
- LOG_DEBUG("impcode: 0x%8.8x", ejtag_info->impcode);
-
+ uint32_t ejtag_version;
+ int retval;
+
+ retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
+
/* get ejtag version */
ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
-
- switch (ejtag_version)
- {
+
+ switch (ejtag_version) {
case 0:
LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
break;
case 3:
LOG_DEBUG("EJTAG: Version 3.1 Detected");
break;
+ case 4:
+ LOG_DEBUG("EJTAG: Version 4.1 Detected");
+ break;
+ case 5:
+ LOG_DEBUG("EJTAG: Version 5.1 Detected");
+ break;
default:
LOG_DEBUG("EJTAG: Unknown Version Detected");
break;
}
-
+ LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
+ ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
+ ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
+ ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
+ ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
+ ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
+ ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
+ ejtag_info->impcode & EJTAG_DCR_MIPS64 ? " MIPS64" : " MIPS32");
+
+ if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
+ LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
+
/* set initial state for ejtag control reg */
ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
-
+ ejtag_info->fast_access_save = -1;
+
+ return ERROR_OK;
+}
+
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
+{
+ struct jtag_tap *tap;
+
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field fields[2];
+ uint8_t spracc = 0;
+ uint8_t t[4] = {0, 0, 0, 0};
+
+ /* fastdata 1-bit register */
+ fields[0].num_bits = 1;
+ fields[0].out_value = &spracc;
+ fields[0].in_value = NULL;
+
+ /* processor access data register 32 bit */
+ fields[1].num_bits = 32;
+ fields[1].out_value = t;
+
+ if (write_t) {
+ fields[1].in_value = NULL;
+ buf_set_u32(t, 0, 32, *data);
+ } else
+ fields[1].in_value = (void *) data;
+
+ jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
+
+ if (!write_t && data)
+ jtag_add_callback(mips_le_to_h_u32,
+ (jtag_callback_data_t) data);
+
+ keep_alive();
+
return ERROR_OK;
}
projects / fw / openocd / blobdiff