struct mips_ejtag *ejtag_info;
};
+static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint8_t *buf);
+static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint16_t *buf);
+static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint32_t *buf);
+static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info,
+ uint32_t addr, uint32_t *buf);
+
+static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint8_t *buf);
+static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint16_t *buf);
+static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int count, uint32_t *buf);
+static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info,
+ uint32_t addr, uint32_t *buf);
+
static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
{
uint32_t ejtag_ctrl;
while (1)
{
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_PRACC)
break;
- LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n");
+ LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR;
}
}
/* Send the data out */
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear the access pending bit (let the processor eat!) */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
- jtag_execute_queue();
-
- return ERROR_OK;
+ return jtag_execute_queue();
}
static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address)
int offset;
struct mips_ejtag *ejtag_info = ctx->ejtag_info;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear access pending bit */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
- jtag_execute_queue();
+ int retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
if ((address >= MIPS32_PRACC_PARAM_IN)
&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
return retval;
address = data = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
/* Check for read or write */
return ERROR_OK;
}
-int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
+static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
{
static const uint32_t code[] = {
/* start: */
return retval;
}
-int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
+static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
{
static const uint32_t code[] = {
/* start: */
return retval;
}
-int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
+static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
{
static const uint32_t code[] = {
/* start: */
return ERROR_OK;
}
-int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
+static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
{
static const uint32_t code[] = {
/* start: */
return ERROR_OK;
}
-int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
+static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
{
static const uint32_t code[] = {
/* start: */
return ERROR_OK;
}
-int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
+static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
{
static const uint32_t code[] = {
/* start: */
return ERROR_OK;
}
-int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
+static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
{
static const uint32_t code[] = {
/* start: */
return ERROR_OK;
}
-int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
+static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
{
static const uint32_t code[] = {
/* start: */
* 3. data ...
*/
int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
- int write, uint32_t addr, int count, uint32_t *buf)
+ int write_t, uint32_t addr, int count, uint32_t *buf)
{
uint32_t handler_code[] = {
/* caution when editing, table is modified below */
if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- if (write)
+ if (write_t)
{
handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */
handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */
}
/* write program into RAM */
- mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code);
+ if (write_t != ejtag_info->fast_access_save)
+ {
+ mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code);
+ /* save previous operation to speed to any consecutive read/writes */
+ ejtag_info->fast_access_save = write_t;
+ }
LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler", __func__, source->address);
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]);
/* Clear the access pending bit (let the processor eat!) */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
}
/* next fetch to dmseg should be in FASTDATA_AREA, check */
address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_FASTDATA_AREA)
/* Send the load start address */
val = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
/* Send the load end address */
val = addr + (count - 1) * 4;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
for (i = 0; i < count; i++)
{
/* Send the data out using fastdata (clears the access pending bit) */
- if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write, buf++)) != ERROR_OK)
+ if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK)
return retval;
}
return retval;
address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_TEXT)