Nico Coesel <ncoesel@dealogic.nl> MIPS32 speedup patches

[fw/openocd] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 9018d85ce07c863c886fb20769bee23386fc833b..7a4dd5e6814b37dad788a3768b1e07521eaa42bc 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -37,14 +37,30 @@ enum
        MIPS32NUMCOREREGS
 };
 
+typedef struct mips32_comparator_s
+{
+       int used;
+       //int type;
+       u32 bp_value;
+       u32 reg_address;
+} mips32_comparator_t;
+
 typedef struct mips32_common_s
 {
-       int common_magic;
+       u32 common_magic;
        void *arch_info;
        reg_cache_t *core_cache;
        mips_ejtag_t ejtag_info;
        u32 core_regs[MIPS32NUMCOREREGS];
        
+       int bp_scanned;
+       int num_inst_bpoints;
+       int num_data_bpoints;
+       int num_inst_bpoints_avail;
+       int num_data_bpoints_avail;
+       mips32_comparator_t *inst_break_list;
+       mips32_comparator_t *data_break_list;
+       
        /* register cache to processor synchronization */
        int (*read_core_reg)(struct target_s *target, int num);
        int (*write_core_reg)(struct target_s *target, int num);
@@ -58,6 +74,7 @@ typedef struct mips32_core_reg_s
 } mips32_core_reg_t;
 
 #define MIPS32_OP_BEQ  0x04
+#define MIPS32_OP_BNE  0x05
 #define MIPS32_OP_ADDI 0x08
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_COP0 0x10
@@ -86,6 +103,7 @@ typedef struct mips32_core_reg_s
 #define MIPS32_AND(reg, off, val)      MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
 #define MIPS32_B(off)                          MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
+#define MIPS32_BNE(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 #define MIPS32_MFC0(gpr, cpr, sel)     MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -100,14 +118,20 @@ typedef struct mips32_core_reg_s
 #define MIPS32_SB(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 #define MIPS32_SH(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 #define MIPS32_SW(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
+
+/* ejtag specific instructions */
 #define MIPS32_DRET                                    0x4200001F
+#define MIPS32_SDBBP                           0x7000003F
+#define MIPS16_SDBBP                           0xE801
 
 extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
 extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int mips32_configure_break_unit(struct target_s *target);
+extern int mips32_examine(struct target_s *target);
 
 extern int mips32_register_commands(struct command_context_s *cmd_ctx);
 extern int mips32_invalidate_core_regs(target_t *target);