+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 by Drasko DRASKOVIC *
* drasko.draskovic@gmail.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
reg_value = mips32->core_regs[num];
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
- mips32->core_cache->reg_list[num].valid = 1;
- mips32->core_cache->reg_list[num].dirty = 0;
+ mips32->core_cache->reg_list[num].valid = true;
+ mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
- mips32->core_cache->reg_list[num].valid = 1;
- mips32->core_cache->reg_list[num].dirty = 0;
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
+ mips32->core_cache->reg_list[num].valid = true;
+ mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
reg_list[i].value = mips32_gdb_dummy_fp_value;
- reg_list[i].valid = 1;
+ reg_list[i].valid = true;
reg_list[i].arch_info = NULL;
register_init_dummy(®_list[i]);
} else {
reg_list[i].value = calloc(1, 4);
- reg_list[i].valid = 0;
+ reg_list[i].valid = false;
reg_list[i].type = &mips32_reg_type;
reg_list[i].arch_info = &arch_info[i];
LOG_ERROR("unable to allocate reg type list");
}
- reg_list[i].dirty = 0;
+ reg_list[i].dirty = false;
reg_list[i].group = mips32_regs[i].group;
reg_list[i].number = i;
}
for (int i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction == PARAM_IN)
+ continue;
retval = target_write_buffer(target, mem_params[i].address,
mem_params[i].size, mem_params[i].value);
if (retval != ERROR_OK)
}
for (int i = 0; i < num_reg_params; i++) {
- struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+ if (reg_params[i].direction == PARAM_IN)
+ continue;
+
+ struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
- struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
mips32->core_cache->reg_list[i].name, context[i]);
buf_set_u32(mips32->core_cache->reg_list[i].value,
0, 32, context[i]);
- mips32->core_cache->reg_list[i].valid = 1;
- mips32->core_cache->reg_list[i].dirty = 1;
+ mips32->core_cache->reg_list[i].valid = true;
+ mips32->core_cache->reg_list[i].dirty = true;
}
}
break; /* no more config registers implemented */
}
else
- return ERROR_OK; /* already succesfully read */
+ return ERROR_OK; /* already successfully read */
- LOG_DEBUG("read %"PRId32" config registers", ejtag_info->config_regs);
+ LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
mips32->isa_imp = MIPS32_MIPS16;
/** Checks whether a memory region is erased. */
int mips32_blank_check_memory(struct target *target,
- target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
+ struct target_memory_check_block *blocks, int num_blocks,
+ uint8_t erased_value)
{
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
int retval = target_write_buffer(target, erase_check_algorithm->address,
sizeof(erase_check_code), erase_check_code_8);
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32;
init_reg_param(®_params[0], "r4", 32, PARAM_OUT);
- buf_set_u32(reg_params[0].value, 0, 32, address);
+ buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
- buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
init_reg_param(®_params[2], "r6", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, erased_value);
erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &mips32_info);
if (retval == ERROR_OK)
- *blank = buf_get_u32(reg_params[2].value, 0, 32);
+ blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+cleanup:
target_free_working_area(target, erase_check_algorithm);
- return retval;
+ if (retval != ERROR_OK)
+ return retval;
+
+ return 1; /* only one block has been checked */
}
-static int mips32_verify_pointer(struct command_context *cmd_ctx,
+static int mips32_verify_pointer(struct command_invocation *cmd,
struct mips32_common *mips32)
{
if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not an MIPS32");
+ command_print(cmd, "target is not an MIPS32");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
- retval = mips32_verify_pointer(CMD_CTX, mips32);
+ retval = mips32_verify_pointer(CMD, mips32);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't access reg %" PRIi32,
+ command_print(CMD,
+ "couldn't access reg %" PRIu32,
cp0_reg);
return ERROR_OK;
}
- command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
} else if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+ command_print(CMD,
+ "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
cp0_reg, cp0_sel);
return ERROR_OK;
}
- command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
}
}
else if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+ command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
ejtag_info->mode = 0;
- command_print(CMD_CTX, "running in legacy mode");
+ command_print(CMD, "running in legacy mode");
} else {
ejtag_info->mode = 1;
- command_print(CMD_CTX, "running in fast queued mode");
+ command_print(CMD, "running in fast queued mode");
}
return ERROR_OK;
projects / fw / openocd / blobdiff