#define MIPS32NUMFPREGS 34 + 18
-u8 mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
+uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
reg_t mips32_gdb_dummy_fp_reg =
{
return retval;
}
-int mips32_set_core_reg(reg_t *reg, u8 *buf)
+int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
{
mips32_core_reg_t *mips32_reg = reg->arch_info;
target_t *target = mips32_reg->target;
- u32 value = buf_get_u32(buf, 0, 32);
+ uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
{
int mips32_read_core_reg(struct target_s *target, int num)
{
- u32 reg_value;
+ uint32_t reg_value;
mips32_core_reg_t *mips_core_reg;
/* get pointers to arch-specific information */
int mips32_write_core_reg(struct target_s *target, int num)
{
- u32 reg_value;
+ uint32_t reg_value;
mips32_core_reg_t *mips_core_reg;
/* get pointers to arch-specific information */
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
mips32->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
mips32->core_cache->reg_list[num].valid = 1;
mips32->core_cache->reg_list[num].dirty = 0;
exit(-1);
}
- LOG_USER("target halted due to %s, pc: 0x%8.8x",
- Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
+ LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
return ERROR_OK;
return ERROR_OK;
}
-int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
{
/*TODO*/
return ERROR_OK;
{
mips32_common_t *mips32 = target->arch_info;
- if (!target->type->examined)
+ if (!target_was_examined(target))
{
- target->type->examined = 1;
+ target_set_examined(target);
/* we will configure later */
mips32->bp_scanned = 0;
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
int retval;
- u32 dcr, bpinfo;
+ uint32_t dcr, bpinfo;
int i;
if (mips32->bp_scanned)
return retval;
}
- LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+ LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
mips32->bp_scanned = 1;
{
int retval;
int update = 0;
- u32 dcr;
+ uint32_t dcr;
/* read debug control register */
if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
if (enable)
{
- if (!(dcr & (1<<4)))
+ if (!(dcr & (1 << 4)))
{
/* enable interrupts */
- dcr |= (1<<4);
+ dcr |= (1 << 4);
update = 1;
}
}
else
{
- if (dcr & (1<<4))
+ if (dcr & (1 << 4))
{
/* disable interrupts */
- dcr &= ~(1<<4);
+ dcr &= ~(1 << 4);
update = 1;
}
}