Transform 'u32' to 'uint32_t' in src/target

[fw/openocd] / src / target / mips32.c

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 084e627681025702f8c29a29dbbf07547ed6868c..5d9f343fb0acbf22397d900254ac5bfc978c255c 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -86,7 +86,7 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 
 #define MIPS32NUMFPREGS 34 + 18
 
-u8 mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
+uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
 
 reg_t mips32_gdb_dummy_fp_reg =
 {
@@ -112,11 +112,11 @@ int mips32_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int mips32_set_core_reg(reg_t *reg, u8 *buf)
+int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
 {
        mips32_core_reg_t *mips32_reg = reg->arch_info;
        target_t *target = mips32_reg->target;
-       u32 value = buf_get_u32(buf, 0, 32);
+       uint32_t value = buf_get_u32(buf, 0, 32);
                
        if (target->state != TARGET_HALTED)
        {
@@ -132,7 +132,7 @@ int mips32_set_core_reg(reg_t *reg, u8 *buf)
 
 int mips32_read_core_reg(struct target_s *target, int num)
 {
-       u32 reg_value;
+       uint32_t reg_value;
        mips32_core_reg_t *mips_core_reg;
        
        /* get pointers to arch-specific information */
@@ -152,7 +152,7 @@ int mips32_read_core_reg(struct target_s *target, int num)
 
 int mips32_write_core_reg(struct target_s *target, int num)
 {
-       u32 reg_value;
+       uint32_t reg_value;
        mips32_core_reg_t *mips_core_reg;
        
        /* get pointers to arch-specific information */
@@ -336,7 +336,7 @@ int mips32_register_commands(struct command_context_s *cmd_ctx)
        return ERROR_OK;
 }
 
-int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
        /*TODO*/
        return ERROR_OK;
@@ -346,9 +346,9 @@ int mips32_examine(struct target_s *target)
 {
        mips32_common_t *mips32 = target->arch_info;
        
-       if (!target->type->examined)
+       if (!target_was_examined(target))
        {
-               target->type->examined = 1;
+               target_set_examined(target);
        
                /* we will configure later */
                mips32->bp_scanned = 0;
@@ -366,7 +366,7 @@ int mips32_configure_break_unit(struct target_s *target)
        /* get pointers to arch-specific information */
        mips32_common_t *mips32 = target->arch_info;
        int retval;
-       u32 dcr, bpinfo;
+       uint32_t dcr, bpinfo;
        int i;
        
        if (mips32->bp_scanned)
@@ -425,7 +425,7 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
 {
        int retval;
        int update = 0;
-       u32 dcr;
+       uint32_t dcr;
        
        /* read debug control register */
        if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)