#define MIPS32NUMFPREGS 34 + 18
-u8 mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
+uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
reg_t mips32_gdb_dummy_fp_reg =
{
return retval;
}
-int mips32_set_core_reg(reg_t *reg, u8 *buf)
+int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
{
mips32_core_reg_t *mips32_reg = reg->arch_info;
target_t *target = mips32_reg->target;
{
mips32_common_t *mips32 = target->arch_info;
- if (!target->type->examined)
+ if (!target_was_examined(target))
{
- target->type->examined = 1;
+ target_set_examined(target);
/* we will configure later */
mips32->bp_scanned = 0;
return ERROR_OK;
}
+
+int mips32_enable_interrupts(struct target_s *target, int enable)
+{
+ int retval;
+ int update = 0;
+ u32 dcr;
+
+ /* read debug control register */
+ if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+ return retval;
+
+ if (enable)
+ {
+ if (!(dcr & (1<<4)))
+ {
+ /* enable interrupts */
+ dcr |= (1<<4);
+ update = 1;
+ }
+ }
+ else
+ {
+ if (dcr & (1<<4))
+ {
+ /* disable interrupts */
+ dcr &= ~(1<<4);
+ update = 1;
+ }
+ }
+
+ if (update)
+ {
+ if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}