Transform 'u8' to 'uint8_t' in src/target

[fw/openocd] / src / target / mips32.c

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 48e2b3427cf2b0c6e6d95a76915807f927ef5c39..138a53553258828b5ae5b594697c4efb4791ee13 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -27,11 +27,7 @@
 #endif
 
 #include "mips32.h"
-#include "jtag.h"
-#include "log.h"
 
-#include <stdlib.h>
-#include <string.h>
 
 char* mips32_core_reg_list[] =
 {
@@ -90,7 +86,7 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 
 #define MIPS32NUMFPREGS 34 + 18
 
-u8 mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
+uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
 
 reg_t mips32_gdb_dummy_fp_reg =
 {
@@ -116,7 +112,7 @@ int mips32_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int mips32_set_core_reg(reg_t *reg, u8 *buf)
+int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
 {
        mips32_core_reg_t *mips32_reg = reg->arch_info;
        target_t *target = mips32_reg->target;
@@ -350,9 +346,9 @@ int mips32_examine(struct target_s *target)
 {
        mips32_common_t *mips32 = target->arch_info;
        
-       if (!target->type->examined)
+       if (!target_was_examined(target))
        {
-               target->type->examined = 1;
+               target_set_examined(target);
        
                /* we will configure later */
                mips32->bp_scanned = 0;
@@ -424,3 +420,41 @@ int mips32_configure_break_unit(struct target_s *target)
        
        return ERROR_OK;
 }
+
+int mips32_enable_interrupts(struct target_s *target, int enable)
+{
+       int retval;
+       int update = 0;
+       u32 dcr;
+       
+       /* read debug control register */
+       if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+               return retval;
+       
+       if (enable)
+       {
+               if (!(dcr & (1<<4)))
+               {
+                       /* enable interrupts */
+                       dcr |= (1<<4);
+                       update = 1;
+               }
+       }
+       else
+       {
+               if (dcr & (1<<4))
+               {
+                       /* disable interrupts */
+                       dcr &= ~(1<<4);
+                       update = 1;
+               }
+       }
+       
+       if (update)
+       {
+               if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
+                       return retval;
+       }
+       
+       return ERROR_OK;
+}