#endif
#include "mips32.h"
-#include "jtag.h"
-#include "log.h"
-#include <stdlib.h>
-#include <string.h>
char* mips32_core_reg_list[] =
{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
"status", "lo", "hi", "badvaddr", "cause", "pc"
};
{37, NULL, NULL},
};
-u8 mips32_gdb_dummy_fsr_value[] = {0, 0, 0, 0};
+/* number of mips dummy fp regs fp0 - fp31 + fsr and fir
+ * we also add 18 unknown registers to handle gdb requests */
-reg_t mips32_gdb_dummy_fsr_reg =
-{
- "GDB dummy floating-point status register", mips32_gdb_dummy_fsr_value, 0, 1, 32, NULL, 0, NULL, 0
-};
+#define MIPS32NUMFPREGS 34 + 18
-u8 mips32_gdb_dummy_fir_value[] = {0, 0, 0, 0};
+uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
-reg_t mips32_gdb_dummy_fir_reg =
+reg_t mips32_gdb_dummy_fp_reg =
{
- "GDB dummy floating-point register", mips32_gdb_dummy_fir_value, 0, 1, 32, NULL, 0, NULL, 0
+ "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0
};
int mips32_core_reg_arch_type = -1;
return retval;
}
-int mips32_set_core_reg(reg_t *reg, u8 *buf)
+int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
{
mips32_core_reg_t *mips32_reg = reg->arch_info;
target_t *target = mips32_reg->target;
mips32_common_t *mips32 = target->arch_info;
int i;
- /* include fsr/fir reg */
- *reg_list_size = MIPS32NUMCOREREGS + 2;
+ /* include floating point registers */
+ *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
for (i = 0; i < MIPS32NUMCOREREGS; i++)
}
/* add dummy floating points regs */
- (*reg_list)[38] = &mips32_gdb_dummy_fsr_reg;
- (*reg_list)[39] = &mips32_gdb_dummy_fir_reg;
-
+ for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
+ {
+ (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
+ }
+
return ERROR_OK;
}
if (mips32_core_reg_arch_type == -1)
mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
- register_init_dummy(&mips32_gdb_dummy_fsr_reg);
- register_init_dummy(&mips32_gdb_dummy_fir_reg);
+ register_init_dummy(&mips32_gdb_dummy_fp_reg);
/* Build the process context cache */
cache->name = "mips32 registers";
return cache;
}
-int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant)
+int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap)
{
target->arch_info = mips32;
mips32->common_magic = MIPS32_COMMON_MAGIC;
- mips32->ejtag_info.chain_pos = chain_pos;
+ /* has breakpoint/watchpint unit been scanned */
+ mips32->bp_scanned = 0;
+ mips32->data_break_list = NULL;
+
+ mips32->ejtag_info.tap = tap;
mips32->read_core_reg = mips32_read_core_reg;
mips32->write_core_reg = mips32_write_core_reg;
/*TODO*/
return ERROR_OK;
}
+
+int mips32_examine(struct target_s *target)
+{
+ mips32_common_t *mips32 = target->arch_info;
+
+ if (!target_was_examined(target))
+ {
+ target_set_examined(target);
+
+ /* we will configure later */
+ mips32->bp_scanned = 0;
+ mips32->num_inst_bpoints = 0;
+ mips32->num_data_bpoints = 0;
+ mips32->num_inst_bpoints_avail = 0;
+ mips32->num_data_bpoints_avail = 0;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_configure_break_unit(struct target_s *target)
+{
+ /* get pointers to arch-specific information */
+ mips32_common_t *mips32 = target->arch_info;
+ int retval;
+ u32 dcr, bpinfo;
+ int i;
+
+ if (mips32->bp_scanned)
+ return ERROR_OK;
+
+ /* get info about breakpoint support */
+ if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+ return retval;
+
+ if (dcr & (1 << 16))
+ {
+ /* get number of inst breakpoints */
+ if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
+ return retval;
+
+ mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
+ mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
+ mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t));
+ for (i = 0; i < mips32->num_inst_bpoints; i++)
+ {
+ mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
+ }
+
+ /* clear IBIS reg */
+ if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
+ return retval;
+ }
+
+ if (dcr & (1 << 17))
+ {
+ /* get number of data breakpoints */
+ if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
+ return retval;
+
+ mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
+ mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
+ mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t));
+ for (i = 0; i < mips32->num_data_bpoints; i++)
+ {
+ mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
+ }
+
+ /* clear DBIS reg */
+ if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
+ return retval;
+ }
+
+ LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+
+ mips32->bp_scanned = 1;
+
+ return ERROR_OK;
+}
+
+int mips32_enable_interrupts(struct target_s *target, int enable)
+{
+ int retval;
+ int update = 0;
+ u32 dcr;
+
+ /* read debug control register */
+ if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+ return retval;
+
+ if (enable)
+ {
+ if (!(dcr & (1<<4)))
+ {
+ /* enable interrupts */
+ dcr |= (1<<4);
+ update = 1;
+ }
+ }
+ else
+ {
+ if (dcr & (1<<4))
+ {
+ /* disable interrupts */
+ dcr &= ~(1<<4);
+ update = 1;
+ }
+ }
+
+ if (update)
+ {
+ if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
projects / fw / openocd / blobdiff