{
int retval = ERROR_OK;
struct x86_32_common *x86_32 = target_to_x86_32(t);
- if (NULL == t->tap) {
+ if (!t->tap) {
retval = ERROR_FAIL;
LOG_ERROR("%s invalid target tap", __func__);
return retval;
int retval = ERROR_OK;
uint64_t data = 0;
struct x86_32_common *x86_32 = target_to_x86_32(t);
- if (NULL == t->tap) {
+ if (!t->tap) {
retval = ERROR_FAIL;
LOG_ERROR("%s invalid target tap", __func__);
return retval;
return retval;
}
}
- if (in != NULL) {
+ if (in) {
if (len >= 8) {
for (int n = (len / 8) - 1 ; n >= 0; n--)
data = (data << 8) + *(in+n);
}
for (i = 0; i < (x86_32->cache->num_regs); i++) {
- x86_32->cache->reg_list[i].dirty = 0;
- x86_32->cache->reg_list[i].valid = 0;
+ x86_32->cache->reg_list[i].dirty = false;
+ x86_32->cache->reg_list[i].valid = false;
}
return err;
}
/*
* we keep reg_cache in sync with hardware at halt/resume time, we avoid
- * writing to real hardware here bacause pm_regs reflects the hardware
+ * writing to real hardware here because pm_regs reflects the hardware
* while we are halted then reg_cache syncs with hw on resume
* TODO - in order for "reg eip force" to work it assume get/set reads
* and writes from hardware, may be other reasons also because generally
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
static const struct reg_arch_type lakemont_reg_type = {
- /* these get called if reg_cache doesnt have a "valid" value
+ /* these get called if reg_cache doesn't have a "valid" value
* of an individual reg eg "reg eip" but not for "reg" block
*/
.get = lakemont_get_core_reg,
struct reg_feature *feature;
int i;
- if (cache == NULL || reg_list == NULL || arch_info == NULL) {
+ if (!cache || !reg_list || !arch_info) {
free(cache);
free(reg_list);
free(arch_info);
reg_list[i].name = regs[i].name;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &lakemont_reg_type;
reg_list[i].arch_info = &arch_info[i];
static int enter_probemode(struct target *t)
{
uint32_t tapstatus = 0;
+ int retries = 100;
+
tapstatus = get_tapstatus(t);
LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
if (tapstatus & TS_PM_BIT) {
scan.out[0] = 1;
if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
return ERROR_FAIL;
- tapstatus = get_tapstatus(t);
- LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
- if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
- return ERROR_OK;
- else {
- LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
- , __func__, tapstatus);
- return ERROR_FAIL;
+
+ while (retries--) {
+ tapstatus = get_tapstatus(t);
+ LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
+ if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
+ return ERROR_OK;
}
+
+ LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
+ , __func__, tapstatus);
+ return ERROR_FAIL;
}
static int exit_probemode(struct target *t)
unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
- if (NOT_AVAIL_REG == regs[i].pm_idx)
+ if (regs[i].pm_idx == NOT_AVAIL_REG)
continue;
err = read_hw_reg(t, regs[i].id, ®val, 1);
if (err != ERROR_OK) {
unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
- if (NOT_AVAIL_REG == regs[i].pm_idx)
+ if (regs[i].pm_idx == NOT_AVAIL_REG)
continue;
err = write_hw_reg(t, i, 0, 1);
if (err != ERROR_OK) {
struct x86_32_common *x86_32 = target_to_x86_32(t);
struct lakemont_core_reg *arch_info;
arch_info = x86_32->cache->reg_list[reg].arch_info;
- x86_32->flush = 0; /* dont flush scans till we have a batch */
+ x86_32->flush = 0; /* don't flush scans till we have a batch */
if (submit_reg_pir(t, reg) != ERROR_OK)
return ERROR_FAIL;
if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
*regval = buf_get_u32(scan.out, 0, 32);
if (cache) {
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
- x86_32->cache->reg_list[reg].valid = 1;
- x86_32->cache->reg_list[reg].dirty = 0;
+ x86_32->cache->reg_list[reg].valid = true;
+ x86_32->cache->reg_list[reg].dirty = false;
}
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
arch_info->op,
regval);
- x86_32->flush = 0; /* dont flush scans till we have a batch */
+ x86_32->flush = 0; /* don't flush scans till we have a batch */
if (submit_reg_pir(t, reg) != ERROR_OK)
return ERROR_FAIL;
if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
/* we are writing from the cache so ensure we reset flags */
if (cache) {
- x86_32->cache->reg_list[reg].dirty = 0;
- x86_32->cache->reg_list[reg].valid = 0;
+ x86_32->cache->reg_list[reg].dirty = false;
+ x86_32->cache->reg_list[reg].valid = false;
}
return ERROR_OK;
}
*/
struct breakpoint *bp = NULL;
bp = breakpoint_find(t, eip-1);
- if (bp != NULL) {
+ if (bp) {
t->debug_reason = DBG_REASON_BREAKPOINT;
if (bp->type == BKPT_SOFT) {
- /* The EIP is now pointing the the next byte after the
+ /* The EIP is now pointing the next byte after the
* breakpoint instruction. This needs to be corrected.
*/
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
- x86_32->cache->reg_list[EIP].dirty = 1;
- x86_32->cache->reg_list[EIP].valid = 1;
+ x86_32->cache->reg_list[EIP].dirty = true;
+ x86_32->cache->reg_list[EIP].valid = true;
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
} else {
/* it's not a hardware breakpoint (checked already in DR6 state)
return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
}
}
+
return ERROR_OK;
}
}
}
-int lakemont_resume(struct target *t, int current, uint32_t address,
+int lakemont_resume(struct target *t, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
{
struct breakpoint *bp = NULL;
/* running away for a software breakpoint needs some special handling */
uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
bp = breakpoint_find(t, eip);
- if (bp != NULL /*&& bp->type == BKPT_SOFT*/) {
+ if (bp /*&& bp->type == BKPT_SOFT*/) {
/* the step will step over the breakpoint */
if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
/* if breakpoints are enabled, we need to redirect these into probe mode */
struct breakpoint *activeswbp = t->breakpoints;
- while (activeswbp != NULL && activeswbp->set == 0)
+ while (activeswbp && activeswbp->set == 0)
activeswbp = activeswbp->next;
struct watchpoint *activehwbp = t->watchpoints;
- while (activehwbp != NULL && activehwbp->set == 0)
+ while (activehwbp && activehwbp->set == 0)
activehwbp = activehwbp->next;
- if (activeswbp != NULL || activehwbp != NULL)
+ if (activeswbp || activehwbp)
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
if (do_resume(t) != ERROR_OK)
return ERROR_FAIL;
}
int lakemont_step(struct target *t, int current,
- uint32_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
bp = breakpoint_find(t, eip);
- if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) {
+ if (retval == ERROR_OK && bp/*&& bp->type == BKPT_SOFT*/) {
/* TODO: This should only be done for software breakpoints.
* Stepping from hardware breakpoints should be possible with the resume flag
* Needs testing.
/* try to re-apply the breakpoint, even of step failed
* TODO: When a bp was set, we should try to stop the target - fix the return above
*/
- if (bp != NULL/*&& bp->type == BKPT_SOFT*/) {
+ if (bp/*&& bp->type == BKPT_SOFT*/) {
/* TODO: This should only be done for software breakpoints.
* Stepping from hardware breakpoints should be possible with the resume flag
* Needs testing.
return retval;
}
-/* TODO - implement resetbreak fully through CLTAP registers */
+static int lakemont_reset_break(struct target *t)
+{
+ struct x86_32_common *x86_32 = target_to_x86_32(t);
+ struct jtag_tap *saved_tap = x86_32->curr_tap;
+ struct scan_field *fields = &scan.field;
+
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("issuing port 0xcf9 reset");
+
+ /* prepare resetbreak setting the proper bits in CLTAPC_CPU_VPREQ */
+ x86_32->curr_tap = jtag_tap_by_position(1);
+ if (!x86_32->curr_tap) {
+ x86_32->curr_tap = saved_tap;
+ LOG_ERROR("%s could not select quark_x10xx.cltap", __func__);
+ return ERROR_FAIL;
+ }
+
+ fields->in_value = NULL;
+ fields->num_bits = 8;
+
+ /* select CLTAPC_CPU_VPREQ instruction*/
+ scan.out[0] = 0x51;
+ fields->out_value = ((uint8_t *)scan.out);
+ jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE);
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ x86_32->curr_tap = saved_tap;
+ LOG_ERROR("%s irscan failed to execute queue", __func__);
+ return retval;
+ }
+
+ /* set enable_preq_on_reset & enable_preq_on_reset2 bits*/
+ scan.out[0] = 0x06;
+ fields->out_value = ((uint8_t *)scan.out);
+ jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE);
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s drscan failed to execute queue", __func__);
+ x86_32->curr_tap = saved_tap;
+ return retval;
+ }
+
+ /* restore current tap */
+ x86_32->curr_tap = saved_tap;
+
+ return ERROR_OK;
+}
+
+/*
+ * If we ever get an adapter with support for PREQ# and PRDY#, we should
+ * update this function to add support for using those two signals.
+ *
+ * Meanwhile, we're assuming that we only support reset break.
+ */
int lakemont_reset_assert(struct target *t)
{
- LOG_DEBUG("-");
+ struct x86_32_common *x86_32 = target_to_x86_32(t);
+ /* write 0x6 to I/O port 0xcf9 to cause the reset */
+ uint8_t cf9_reset_val = 0x6;
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ if (t->state != TARGET_HALTED) {
+ LOG_DEBUG("target must be halted first");
+ retval = lakemont_halt(t);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not halt target");
+ return retval;
+ }
+ x86_32->forced_halt_for_reset = true;
+ }
+
+ if (t->reset_halt) {
+ retval = lakemont_reset_break(t);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ retval = x86_32_common_write_io(t, 0xcf9, BYTE, &cf9_reset_val);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not write to port 0xcf9");
+ return retval;
+ }
+
+ if (!t->reset_halt && x86_32->forced_halt_for_reset) {
+ x86_32->forced_halt_for_reset = false;
+ retval = lakemont_resume(t, true, 0x00, false, true);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* remove breakpoints and watchpoints */
+ x86_32_common_reset_breakpoints_watchpoints(t);
+
return ERROR_OK;
}
int lakemont_reset_deassert(struct target *t)
{
- LOG_DEBUG("-");
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ if (target_was_examined(t)) {
+ retval = lakemont_poll(t);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ if (t->reset_halt) {
+ /* entered PM after reset, update the state */
+ retval = lakemont_update_after_probemode_entry(t);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not update state after probemode entry");
+ return retval;
+ }
+
+ if (t->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(t));
+ if (target_was_examined(t)) {
+ retval = target_halt(t);
+ if (retval != ERROR_OK)
+ return retval;
+ } else {
+ t->state = TARGET_UNKNOWN;
+ }
+ }
+ }
+
return ERROR_OK;
}
projects / fw / openocd / blobdiff