#include "config.h"
#endif
+#include "jtag/interface.h"
#include "jtag/jtag.h"
#include "jtag/hla/hla_transport.h"
#include "jtag/hla/hla_interface.h"
}
static int adapter_load_core_reg_u32(struct target *target,
- uint32_t num, uint32_t *value)
+ uint32_t regsel, uint32_t *value)
{
int retval;
struct hl_interface_s *adapter = target_to_adapter(target);
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
- switch (num) {
- case 0 ... 18:
+ switch (regsel) {
+ case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
/* read a normal core register */
- retval = adapter->layout->api->read_reg(adapter->handle, num, value);
+ retval = adapter->layout->api->read_reg(adapter->handle, regsel, value);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
+ LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
- case ARMV7M_FPSCR:
+ case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
- retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
break;
- case ARMV7M_S0 ... ARMV7M_S31:
+ case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
- retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
- (int)(num - ARMV7M_S0), *value);
+ (int)(regsel - ARMV7M_REGSEL_S0), *value);
break;
case ARMV7M_PRIMASK:
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
- retval = adapter->layout->api->read_reg(adapter->handle, 20, value);
+ retval = adapter->layout->api->read_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, value);
if (retval != ERROR_OK)
return retval;
- switch (num) {
+ switch (regsel) {
case ARMV7M_PRIMASK:
*value = buf_get_u32((uint8_t *) value, 0, 1);
break;
break;
case ARMV7M_CONTROL:
- *value = buf_get_u32((uint8_t *) value, 24, 2);
+ *value = buf_get_u32((uint8_t *) value, 24, 3);
break;
}
- LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
- (int)num, *value);
+ LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "",
+ regsel, *value);
break;
default:
}
static int adapter_store_core_reg_u32(struct target *target,
- uint32_t num, uint32_t value)
+ uint32_t regsel, uint32_t value)
{
int retval;
uint32_t reg;
LOG_DEBUG("%s", __func__);
- /* NOTE: we "know" here that the register identifiers used
- * in the v7m header match the Cortex-M3 Debug Core Register
- * Selector values for R0..R15, xPSR, MSP, and PSP.
- */
- switch (num) {
- case 0 ... 18:
- retval = adapter->layout->api->write_reg(adapter->handle, num, value);
+ switch (regsel) {
+ case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
+ retval = adapter->layout->api->write_reg(adapter->handle, regsel, value);
if (retval != ERROR_OK) {
struct reg *r;
LOG_ERROR("JTAG failure");
- r = armv7m->arm.core_cache->reg_list + num;
+ r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+ LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
break;
- case ARMV7M_FPSCR:
+ case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
break;
- case ARMV7M_S0 ... ARMV7M_S31:
+ case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
- (int)(num - ARMV7M_S0), value);
+ (int)(regsel - ARMV7M_REGSEL_S0), value);
break;
case ARMV7M_PRIMASK:
* it was removed from r1 docs, but still works.
*/
- adapter->layout->api->read_reg(adapter->handle, 20, ®);
+ adapter->layout->api->read_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, ®);
- switch (num) {
+ switch (regsel) {
case ARMV7M_PRIMASK:
buf_set_u32((uint8_t *) ®, 0, 1, value);
break;
break;
case ARMV7M_CONTROL:
- buf_set_u32((uint8_t *) ®, 24, 2, value);
+ buf_set_u32((uint8_t *) ®, 24, 3, value);
break;
}
- adapter->layout->api->write_reg(adapter->handle, 20, reg);
+ adapter->layout->api->write_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, reg);
- LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
+ LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
break;
default:
uint32_t i;
for (i = 0; i < (size * 4); i++) {
- hl_dcc_read(hl_if, &data, &ctrl);
+ int err = hl_dcc_read(hl_if, &data, &ctrl);
+ if (err != ERROR_OK)
+ return err;
+
buffer[i] = data;
}
static int hl_handle_target_request(void *priv)
{
struct target *target = priv;
+ int err;
+
if (!target_was_examined(target))
return ERROR_OK;
struct hl_interface_s *hl_if = target_to_adapter(target);
uint8_t data;
uint8_t ctrl;
- hl_dcc_read(hl_if, &data, &ctrl);
+ err = hl_dcc_read(hl_if, &data, &ctrl);
+ if (err != ERROR_OK)
+ return err;
/* check if we have data */
if (ctrl & (1 << 0)) {
/* we assume target is quick enough */
request = data;
- hl_dcc_read(hl_if, &data, &ctrl);
+ err = hl_dcc_read(hl_if, &data, &ctrl);
+ if (err != ERROR_OK)
+ return err;
+
request |= (data << 8);
- hl_dcc_read(hl_if, &data, &ctrl);
+ err = hl_dcc_read(hl_if, &data, &ctrl);
+ if (err != ERROR_OK)
+ return err;
+
request |= (data << 16);
- hl_dcc_read(hl_if, &data, &ctrl);
+ err = hl_dcc_read(hl_if, &data, &ctrl);
+ if (err != ERROR_OK)
+ return err;
+
request |= (data << 24);
target_request(target, request);
}
armv7m->examine_debug_reason = adapter_examine_debug_reason;
armv7m->stlink = true;
- target_register_timer_callback(hl_handle_target_request, 1, 1, target);
+ target_register_timer_callback(hl_handle_target_request, 1,
+ TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
Jim_Interp *interp)
{
LOG_DEBUG("%s", __func__);
+ struct adiv5_private_config *pc = target->private_config;
+ if (pc != NULL && pc->ap_num > 0) {
+ LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
-
- if (!cortex_m)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (cortex_m == NULL) {
+ LOG_ERROR("No memory creating target");
+ return ERROR_FAIL;
+ }
adapter_init_arch_info(target, cortex_m, target->tap);
arm->map = armv7m_msp_reg_map;
} else {
unsigned control = buf_get_u32(arm->core_cache
- ->reg_list[ARMV7M_CONTROL].value, 0, 2);
+ ->reg_list[ARMV7M_CONTROL].value, 0, 3);
/* is this thread privileged? */
arm->core_mode = control & 1
if (prev_target_state == state)
return ERROR_OK;
+ if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING)
+ return ERROR_OK;
+
target->state = state;
if (state == TARGET_HALTED) {
return ERROR_OK;
}
-static int adapter_assert_reset(struct target *target)
+static int hl_assert_reset(struct target *target)
{
int res = ERROR_OK;
struct hl_interface_s *adapter = target_to_adapter(target);
if ((jtag_reset_config & RESET_HAS_SRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
- jtag_add_reset(0, 1);
- res = adapter->layout->api->assert_srst(adapter->handle, 0);
+ res = adapter_assert_reset();
srst_asserted = true;
}
if (jtag_reset_config & RESET_HAS_SRST) {
if (!srst_asserted) {
- jtag_add_reset(0, 1);
- res = adapter->layout->api->assert_srst(adapter->handle, 0);
+ res = adapter_assert_reset();
}
if (res == ERROR_COMMAND_NOTFOUND)
LOG_ERROR("Hardware srst not supported, falling back to software reset");
return ERROR_OK;
}
-static int adapter_deassert_reset(struct target *target)
+static int hl_deassert_reset(struct target *target)
{
- struct hl_interface_s *adapter = target_to_adapter(target);
-
enum reset_types jtag_reset_config = jtag_get_reset_config();
LOG_DEBUG("%s", __func__);
if (jtag_reset_config & RESET_HAS_SRST)
- adapter->layout->api->assert_srst(adapter->handle, 1);
-
- /* virtual deassert reset, we need it for the internal
- * jtag state machine
- */
- jtag_add_reset(0, 0);
+ adapter_deassert_reset();
target->savedDCRDR = 0; /* clear both DCC busy bits on initial resume */
.init_target = adapter_init_target,
.deinit_target = cortex_m_deinit_target,
.target_create = adapter_target_create,
+ .target_jim_configure = adiv5_jim_configure,
.examine = cortex_m_examine,
.commands = adapter_command_handlers,
.arch_state = armv7m_arch_state,
.target_request_data = hl_target_request_data,
- .assert_reset = adapter_assert_reset,
- .deassert_reset = adapter_deassert_reset,
+ .assert_reset = hl_assert_reset,
+ .deassert_reset = hl_deassert_reset,
.halt = adapter_halt,
.resume = adapter_resume,
.step = adapter_step,
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
.read_memory = adapter_read_memory,
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