armv7m_trace: get rid of the old tpiu code
[fw/openocd] / src / target / hla_target.c
index a65ba805e4ff991874a618c8aeb720b0c074b263..ca8b5874afd9baba202bba390dc3bb1649d10b80 100644 (file)
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
 
+#include "jtag/interface.h"
 #include "jtag/jtag.h"
 #include "jtag/hla/hla_transport.h"
 #include "jtag/hla/hla_interface.h"
@@ -40,6 +39,7 @@
 #include "cortex_m.h"
 #include "arm_semihosting.h"
 #include "target_request.h"
+#include <rtt/rtt.h>
 
 #define savedDCRDR  dbgbase  /* FIXME: using target->dbgbase to preserve DCRDR */
 
@@ -52,198 +52,17 @@ static inline struct hl_interface_s *target_to_adapter(struct target *target)
 }
 
 static int adapter_load_core_reg_u32(struct target *target,
-               uint32_t num, uint32_t *value)
+               uint32_t regsel, uint32_t *value)
 {
-       int retval;
        struct hl_interface_s *adapter = target_to_adapter(target);
-
-       LOG_DEBUG("%s", __func__);
-
-       /* NOTE:  we "know" here that the register identifiers used
-        * in the v7m header match the Cortex-M3 Debug Core Register
-        * Selector values for R0..R15, xPSR, MSP, and PSP.
-        */
-       switch (num) {
-       case 0 ... 18:
-               /* read a normal core register */
-               retval = adapter->layout->api->read_reg(adapter->fd, num, value);
-
-               if (retval != ERROR_OK) {
-                       LOG_ERROR("JTAG failure %i", retval);
-                       return ERROR_JTAG_DEVICE_ERROR;
-               }
-               LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
-               break;
-
-       case ARMV7M_FPSID:
-       case ARMV7M_FPEXC:
-               *value = 0;
-               break;
-
-       case ARMV7M_FPSCR:
-               /* Floating-point Status and Registers */
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
-               if (retval != ERROR_OK)
-                       return retval;
-               retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
-               if (retval != ERROR_OK)
-                       return retval;
-               LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
-               break;
-
-       case ARMV7M_S0 ... ARMV7M_S31:
-               /* Floating-point Status and Registers */
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
-               if (retval != ERROR_OK)
-                       return retval;
-               retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
-               if (retval != ERROR_OK)
-                       return retval;
-               LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
-               break;
-
-       case ARMV7M_D0 ... ARMV7M_D15:
-               value = 0;
-               break;
-
-       case ARMV7M_PRIMASK:
-       case ARMV7M_BASEPRI:
-       case ARMV7M_FAULTMASK:
-       case ARMV7M_CONTROL:
-               /* Cortex-M3 packages these four registers as bitfields
-                * in one Debug Core register.  So say r0 and r2 docs;
-                * it was removed from r1 docs, but still works.
-                */
-               retval = adapter->layout->api->read_reg(adapter->fd, 20, value);
-               if (retval != ERROR_OK)
-                       return retval;
-
-               switch (num) {
-               case ARMV7M_PRIMASK:
-                       *value = buf_get_u32((uint8_t *) value, 0, 1);
-                       break;
-
-               case ARMV7M_BASEPRI:
-                       *value = buf_get_u32((uint8_t *) value, 8, 8);
-                       break;
-
-               case ARMV7M_FAULTMASK:
-                       *value = buf_get_u32((uint8_t *) value, 16, 1);
-                       break;
-
-               case ARMV7M_CONTROL:
-                       *value = buf_get_u32((uint8_t *) value, 24, 2);
-                       break;
-               }
-
-               LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
-                         (int)num, *value);
-               break;
-
-       default:
-               return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
+       return adapter->layout->api->read_reg(adapter->handle, regsel, value);
 }
 
 static int adapter_store_core_reg_u32(struct target *target,
-               uint32_t num, uint32_t value)
+               uint32_t regsel, uint32_t value)
 {
-       int retval;
-       uint32_t reg;
-       struct armv7m_common *armv7m = target_to_armv7m(target);
        struct hl_interface_s *adapter = target_to_adapter(target);
-
-       LOG_DEBUG("%s", __func__);
-
-       /* NOTE:  we "know" here that the register identifiers used
-        * in the v7m header match the Cortex-M3 Debug Core Register
-        * Selector values for R0..R15, xPSR, MSP, and PSP.
-        */
-       switch (num) {
-       case 0 ... 18:
-               retval = adapter->layout->api->write_reg(adapter->fd, num, value);
-
-               if (retval != ERROR_OK) {
-                       struct reg *r;
-
-                       LOG_ERROR("JTAG failure");
-                       r = armv7m->arm.core_cache->reg_list + num;
-                       r->dirty = r->valid;
-                       return ERROR_JTAG_DEVICE_ERROR;
-               }
-               LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
-               break;
-
-       case ARMV7M_FPSID:
-       case ARMV7M_FPEXC:
-               break;
-
-       case ARMV7M_FPSCR:
-               /* Floating-point Status and Registers */
-               retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
-               if (retval != ERROR_OK)
-                       return retval;
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
-               if (retval != ERROR_OK)
-                       return retval;
-               LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
-               break;
-
-       case ARMV7M_S0 ... ARMV7M_S31:
-               /* Floating-point Status and Registers */
-               retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
-               if (retval != ERROR_OK)
-                       return retval;
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
-               if (retval != ERROR_OK)
-                       return retval;
-               LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
-               break;
-
-       case ARMV7M_D0 ... ARMV7M_D15:
-               break;
-
-       case ARMV7M_PRIMASK:
-       case ARMV7M_BASEPRI:
-       case ARMV7M_FAULTMASK:
-       case ARMV7M_CONTROL:
-               /* Cortex-M3 packages these four registers as bitfields
-                * in one Debug Core register.  So say r0 and r2 docs;
-                * it was removed from r1 docs, but still works.
-                */
-
-               adapter->layout->api->read_reg(adapter->fd, 20, &reg);
-
-               switch (num) {
-               case ARMV7M_PRIMASK:
-                       buf_set_u32((uint8_t *) &reg, 0, 1, value);
-                       break;
-
-               case ARMV7M_BASEPRI:
-                       buf_set_u32((uint8_t *) &reg, 8, 8, value);
-                       break;
-
-               case ARMV7M_FAULTMASK:
-                       buf_set_u32((uint8_t *) &reg, 16, 1, value);
-                       break;
-
-               case ARMV7M_CONTROL:
-                       buf_set_u32((uint8_t *) &reg, 24, 2, value);
-                       break;
-               }
-
-               adapter->layout->api->write_reg(adapter->fd, 20, reg);
-
-               LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
-               break;
-
-       default:
-               return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
+       return adapter->layout->api->write_reg(adapter->handle, regsel, value);
 }
 
 static int adapter_examine_debug_reason(struct target *target)
@@ -259,7 +78,7 @@ static int adapter_examine_debug_reason(struct target *target)
 static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl)
 {
        uint16_t dcrdr;
-       int retval = hl_if->layout->api->read_mem(hl_if->fd,
+       int retval = hl_if->layout->api->read_mem(hl_if->handle,
                        DCB_DCRDR, 1, sizeof(dcrdr), (uint8_t *)&dcrdr);
        if (retval == ERROR_OK) {
            *ctrl = (uint8_t)dcrdr;
@@ -272,7 +91,7 @@ static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ct
                         * to signify we have read data */
                        /* atomically clear just the byte containing the busy bit */
                        static const uint8_t zero;
-                       retval = hl_if->layout->api->write_mem(hl_if->fd, DCB_DCRDR, 1, 1, &zero);
+                       retval = hl_if->layout->api->write_mem(hl_if->handle, DCB_DCRDR, 1, 1, &zero);
                }
        }
        return retval;
@@ -287,7 +106,10 @@ static int hl_target_request_data(struct target *target,
        uint32_t i;
 
        for (i = 0; i < (size * 4); i++) {
-               hl_dcc_read(hl_if, &data, &ctrl);
+               int err = hl_dcc_read(hl_if, &data, &ctrl);
+               if (err != ERROR_OK)
+                       return err;
+
                buffer[i] = data;
        }
 
@@ -297,6 +119,8 @@ static int hl_target_request_data(struct target *target,
 static int hl_handle_target_request(void *priv)
 {
        struct target *target = priv;
+       int err;
+
        if (!target_was_examined(target))
                return ERROR_OK;
        struct hl_interface_s *hl_if = target_to_adapter(target);
@@ -308,7 +132,9 @@ static int hl_handle_target_request(void *priv)
                uint8_t data;
                uint8_t ctrl;
 
-               hl_dcc_read(hl_if, &data, &ctrl);
+               err = hl_dcc_read(hl_if, &data, &ctrl);
+               if (err != ERROR_OK)
+                       return err;
 
                /* check if we have data */
                if (ctrl & (1 << 0)) {
@@ -316,11 +142,20 @@ static int hl_handle_target_request(void *priv)
 
                        /* we assume target is quick enough */
                        request = data;
-                       hl_dcc_read(hl_if, &data, &ctrl);
+                       err = hl_dcc_read(hl_if, &data, &ctrl);
+                       if (err != ERROR_OK)
+                               return err;
+
                        request |= (data << 8);
-                       hl_dcc_read(hl_if, &data, &ctrl);
+                       err = hl_dcc_read(hl_if, &data, &ctrl);
+                       if (err != ERROR_OK)
+                               return err;
+
                        request |= (data << 16);
-                       hl_dcc_read(hl_if, &data, &ctrl);
+                       err = hl_dcc_read(hl_if, &data, &ctrl);
+                       if (err != ERROR_OK)
+                               return err;
+
                        request |= (data << 24);
                        target_request(target, request);
                }
@@ -330,14 +165,14 @@ static int hl_handle_target_request(void *priv)
 }
 
 static int adapter_init_arch_info(struct target *target,
-                                      struct cortex_m3_common *cortex_m3,
+                                      struct cortex_m_common *cortex_m,
                                       struct jtag_tap *tap)
 {
        struct armv7m_common *armv7m;
 
        LOG_DEBUG("%s", __func__);
 
-       armv7m = &cortex_m3->armv7m;
+       armv7m = &cortex_m->armv7m;
        armv7m_init_arch_info(target, armv7m);
 
        armv7m->load_core_reg_u32 = adapter_load_core_reg_u32;
@@ -346,7 +181,8 @@ static int adapter_init_arch_info(struct target *target,
        armv7m->examine_debug_reason = adapter_examine_debug_reason;
        armv7m->stlink = true;
 
-       target_register_timer_callback(hl_handle_target_request, 1, 1, target);
+       target_register_timer_callback(hl_handle_target_request, 1,
+               TARGET_TIMER_TYPE_PERIODIC, target);
 
        return ERROR_OK;
 }
@@ -357,7 +193,7 @@ static int adapter_init_target(struct command_context *cmd_ctx,
        LOG_DEBUG("%s", __func__);
 
        armv7m_build_reg_cache(target);
-
+       arm_semihosting_init(target);
        return ERROR_OK;
 }
 
@@ -365,13 +201,19 @@ static int adapter_target_create(struct target *target,
                Jim_Interp *interp)
 {
        LOG_DEBUG("%s", __func__);
-
-       struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
-
-       if (!cortex_m3)
+       struct adiv5_private_config *pc = target->private_config;
+       if (pc != NULL && pc->ap_num > 0) {
+               LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
                return ERROR_COMMAND_SYNTAX_ERROR;
+       }
 
-       adapter_init_arch_info(target, cortex_m3, target->tap);
+       struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
+       if (cortex_m == NULL) {
+               LOG_ERROR("No memory creating target");
+               return ERROR_FAIL;
+       }
+
+       adapter_init_arch_info(target, cortex_m, target->tap);
 
        return ERROR_OK;
 }
@@ -412,7 +254,7 @@ static int adapter_debug_entry(struct target *target)
        adapter_load_context(target);
 
        /* make sure we clear the vector catch bit */
-       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
+       adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
 
        r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
@@ -425,7 +267,7 @@ static int adapter_debug_entry(struct target *target)
                arm->map = armv7m_msp_reg_map;
        } else {
                unsigned control = buf_get_u32(arm->core_cache
-                               ->reg_list[ARMV7M_CONTROL].value, 0, 2);
+                               ->reg_list[ARMV7M_CONTROL].value, 0, 3);
 
                /* is this thread privileged? */
                arm->core_mode = control & 1
@@ -443,7 +285,7 @@ static int adapter_debug_entry(struct target *target)
 
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
                arm_mode_name(arm->core_mode),
-               *(uint32_t *)(arm->pc->value),
+               buf_get_u32(arm->pc->value, 0, 32),
                target_state_name(target));
 
        return retval;
@@ -456,18 +298,22 @@ static int adapter_poll(struct target *target)
        struct armv7m_common *armv7m = target_to_armv7m(target);
        enum target_state prev_target_state = target->state;
 
-       state = adapter->layout->api->state(adapter->fd);
+       state = adapter->layout->api->state(adapter->handle);
 
        if (state == TARGET_UNKNOWN) {
                LOG_ERROR("jtag status contains invalid mode value - communication failure");
                return ERROR_TARGET_FAILURE;
        }
 
-       if (target->state == state)
+       if (prev_target_state == state)
                return ERROR_OK;
 
+       if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING)
+               return ERROR_OK;
+
+       target->state = state;
+
        if (state == TARGET_HALTED) {
-               target->state = state;
 
                int retval = adapter_debug_entry(target);
                if (retval != ERROR_OK)
@@ -482,13 +328,13 @@ static int adapter_poll(struct target *target)
                        target_call_event_callbacks(target, TARGET_EVENT_HALTED);
                }
 
-               LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+               LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
        }
 
        return ERROR_OK;
 }
 
-static int adapter_assert_reset(struct target *target)
+static int hl_assert_reset(struct target *target)
 {
        int res = ERROR_OK;
        struct hl_interface_s *adapter = target_to_adapter(target);
@@ -503,23 +349,21 @@ static int adapter_assert_reset(struct target *target)
 
        if ((jtag_reset_config & RESET_HAS_SRST) &&
            (jtag_reset_config & RESET_SRST_NO_GATING)) {
-               jtag_add_reset(0, 1);
-               res = adapter->layout->api->assert_srst(adapter->fd, 0);
+               res = adapter_assert_reset();
                srst_asserted = true;
        }
 
-       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
+       adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 
        /* only set vector catch if halt is requested */
        if (target->reset_halt)
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET);
+               adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);
        else
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
+               adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
 
        if (jtag_reset_config & RESET_HAS_SRST) {
                if (!srst_asserted) {
-                       jtag_add_reset(0, 1);
-                       res = adapter->layout->api->assert_srst(adapter->fd, 0);
+                       res = adapter_assert_reset();
                }
                if (res == ERROR_COMMAND_NOTFOUND)
                        LOG_ERROR("Hardware srst not supported, falling back to software reset");
@@ -531,10 +375,10 @@ static int adapter_assert_reset(struct target *target)
 
        if (use_srst_fallback) {
                /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
-               adapter->layout->api->write_debug_reg(adapter->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+               adapter->layout->api->write_debug_reg(adapter->handle, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
        }
 
-       res = adapter->layout->api->reset(adapter->fd);
+       res = adapter->layout->api->reset(adapter->handle);
 
        if (res != ERROR_OK)
                return res;
@@ -552,21 +396,14 @@ static int adapter_assert_reset(struct target *target)
        return ERROR_OK;
 }
 
-static int adapter_deassert_reset(struct target *target)
+static int hl_deassert_reset(struct target *target)
 {
-       struct hl_interface_s *adapter = target_to_adapter(target);
-
        enum reset_types jtag_reset_config = jtag_get_reset_config();
 
        LOG_DEBUG("%s", __func__);
 
        if (jtag_reset_config & RESET_HAS_SRST)
-               adapter->layout->api->assert_srst(adapter->fd, 1);
-
-       /* virtual deassert reset, we need it for the internal
-        * jtag state machine
-        */
-       jtag_add_reset(0, 0);
+               adapter_deassert_reset();
 
        target->savedDCRDR = 0;  /* clear both DCC busy bits on initial resume */
 
@@ -588,7 +425,7 @@ static int adapter_halt(struct target *target)
        if (target->state == TARGET_UNKNOWN)
                LOG_WARNING("target was in unknown state when halt was requested");
 
-       res = adapter->layout->api->halt(adapter->fd);
+       res = adapter->layout->api->halt(adapter->handle);
 
        if (res != ERROR_OK)
                return res;
@@ -599,7 +436,7 @@ static int adapter_halt(struct target *target)
 }
 
 static int adapter_resume(struct target *target, int current,
-               uint32_t address, int handle_breakpoints,
+               target_addr_t address, int handle_breakpoints,
                int debug_execution)
 {
        int res;
@@ -609,8 +446,8 @@ static int adapter_resume(struct target *target, int current,
        struct breakpoint *breakpoint = NULL;
        struct reg *pc;
 
-       LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address,
-                       handle_breakpoints, debug_execution);
+       LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
+                       address, handle_breakpoints, debug_execution);
 
        if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
@@ -619,8 +456,8 @@ static int adapter_resume(struct target *target, int current,
 
        if (!debug_execution) {
                target_free_all_working_areas(target);
-               cortex_m3_enable_breakpoints(target);
-               cortex_m3_enable_watchpoints(target);
+               cortex_m_enable_breakpoints(target);
+               cortex_m_enable_watchpoints(target);
        }
 
        pc = armv7m->arm.pc;
@@ -657,21 +494,21 @@ static int adapter_resume(struct target *target, int current,
                /* Single step past breakpoint at current address */
                breakpoint = breakpoint_find(target, resume_pc);
                if (breakpoint) {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
+                       LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
                                        breakpoint->address,
                                        breakpoint->unique_id);
-                       cortex_m3_unset_breakpoint(target, breakpoint);
+                       cortex_m_unset_breakpoint(target, breakpoint);
 
-                       res = adapter->layout->api->step(adapter->fd);
+                       res = adapter->layout->api->step(adapter->handle);
 
                        if (res != ERROR_OK)
                                return res;
 
-                       cortex_m3_set_breakpoint(target, breakpoint);
+                       cortex_m_set_breakpoint(target, breakpoint);
                }
        }
 
-       res = adapter->layout->api->run(adapter->fd);
+       res = adapter->layout->api->run(adapter->handle);
 
        if (res != ERROR_OK)
                return res;
@@ -690,7 +527,7 @@ static int adapter_resume(struct target *target, int current,
 }
 
 static int adapter_step(struct target *target, int current,
-               uint32_t address, int handle_breakpoints)
+               target_addr_t address, int handle_breakpoints)
 {
        int res;
        struct hl_interface_s *adapter = target_to_adapter(target);
@@ -718,7 +555,7 @@ static int adapter_step(struct target *target, int current,
        if (handle_breakpoints) {
                breakpoint = breakpoint_find(target, pc_value);
                if (breakpoint)
-                       cortex_m3_unset_breakpoint(target, breakpoint);
+                       cortex_m_unset_breakpoint(target, breakpoint);
        }
 
        armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
@@ -734,7 +571,7 @@ static int adapter_step(struct target *target, int current,
 
        target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
-       res = adapter->layout->api->step(adapter->fd);
+       res = adapter->layout->api->step(adapter->handle);
 
        if (res != ERROR_OK)
                return res;
@@ -743,17 +580,17 @@ static int adapter_step(struct target *target, int current,
        register_cache_invalidate(armv7m->arm.core_cache);
 
        if (breakpoint)
-               cortex_m3_set_breakpoint(target, breakpoint);
+               cortex_m_set_breakpoint(target, breakpoint);
 
        adapter_debug_entry(target);
        target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
-       LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+       LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
 
        return ERROR_OK;
 }
 
-static int adapter_read_memory(struct target *target, uint32_t address,
+static int adapter_read_memory(struct target *target, target_addr_t address,
                uint32_t size, uint32_t count,
                uint8_t *buffer)
 {
@@ -762,12 +599,13 @@ static int adapter_read_memory(struct target *target, uint32_t address,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
+       LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
+                         __func__, address, size, count);
 
-       return adapter->layout->api->read_mem(adapter->fd, address, size, count, buffer);
+       return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer);
 }
 
-static int adapter_write_memory(struct target *target, uint32_t address,
+static int adapter_write_memory(struct target *target, target_addr_t address,
                uint32_t size, uint32_t count,
                const uint8_t *buffer)
 {
@@ -776,15 +614,27 @@ static int adapter_write_memory(struct target *target, uint32_t address,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
+       LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
+                         __func__, address, size, count);
 
-       return adapter->layout->api->write_mem(adapter->fd, address, size, count, buffer);
+       return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer);
 }
 
 static const struct command_registration adapter_command_handlers[] = {
        {
                .chain = arm_command_handlers,
        },
+       {
+               .chain = armv7m_trace_command_handlers,
+       },
+       {
+               .chain = rtt_target_command_handlers,
+       },
+       /* START_DEPRECATED_TPIU */
+       {
+               .chain = arm_tpiu_deprecated_command_handlers,
+       },
+       /* END_DEPRECATED_TPIU */
        COMMAND_REGISTRATION_DONE
 };
 
@@ -793,21 +643,24 @@ struct target_type hla_target = {
        .deprecated_name = "stm32_stlink",
 
        .init_target = adapter_init_target,
+       .deinit_target = cortex_m_deinit_target,
        .target_create = adapter_target_create,
-       .examine = cortex_m3_examine,
+       .target_jim_configure = adiv5_jim_configure,
+       .examine = cortex_m_examine,
        .commands = adapter_command_handlers,
 
        .poll = adapter_poll,
        .arch_state = armv7m_arch_state,
 
        .target_request_data = hl_target_request_data,
-       .assert_reset = adapter_assert_reset,
-       .deassert_reset = adapter_deassert_reset,
+       .assert_reset = hl_assert_reset,
+       .deassert_reset = hl_deassert_reset,
 
        .halt = adapter_halt,
        .resume = adapter_resume,
        .step = adapter_step,
 
+       .get_gdb_arch = arm_get_gdb_arch,
        .get_gdb_reg_list = armv7m_get_gdb_reg_list,
 
        .read_memory = adapter_read_memory,
@@ -819,8 +672,9 @@ struct target_type hla_target = {
        .start_algorithm = armv7m_start_algorithm,
        .wait_algorithm = armv7m_wait_algorithm,
 
-       .add_breakpoint = cortex_m3_add_breakpoint,
-       .remove_breakpoint = cortex_m3_remove_breakpoint,
-       .add_watchpoint = cortex_m3_add_watchpoint,
-       .remove_watchpoint = cortex_m3_remove_watchpoint,
+       .add_breakpoint = cortex_m_add_breakpoint,
+       .remove_breakpoint = cortex_m_remove_breakpoint,
+       .add_watchpoint = cortex_m_add_watchpoint,
+       .remove_watchpoint = cortex_m_remove_watchpoint,
+       .profiling = cortex_m_profiling,
 };