int feroceon_assert_reset(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int ud = arm7_9->use_dbgrq;
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_branch_resume(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
{
LOG_DEBUG("-");
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int err;
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_set_dbgrq(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* set a breakpoint there */
void feroceon_disable_single_step(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
void feroceon_common_setup(struct target_s *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
int feroceon_examine(struct target_s *target)
{
- armv4_5_common_t *armv4_5;
+ struct arm *armv4_5;
struct arm7_9_common *arm7_9;
int retval;