drivers/ft232r: Group adapter commands

[fw/openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 21963e55ed515177053f83c0438e3c0111bf104a..bbb793aaa7e6c4b820a3daaed22e97917dfc469d 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -37,7 +37,7 @@
  * - asserting DBGRQ doesn't work if target is looping on the undef vector
  *
  * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
- *   not at the top, and rather meaningless due to existing discrepencies
+ *   not at the top, and rather meaningless due to existing discrepancies
  *
  * - the DCC channel is half duplex (only one FIFO for both directions) with
  *   seemingly no proper flow control.
@@ -373,14 +373,14 @@ static void feroceon_branch_resume_thumb(struct target *target)
 }
 
 static int feroceon_read_cp15(struct target *target, uint32_t op1,
-               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+               uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
 {
        struct arm *arm = target->arch_info;
        struct arm7_9_common *arm7_9 = arm->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int err;
 
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, crn, crm, op2), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
        err = arm7_9_execute_sys_speed(target);
        if (err != ERROR_OK)
@@ -396,7 +396,7 @@ static int feroceon_read_cp15(struct target *target, uint32_t op1,
 }
 
 static int feroceon_write_cp15(struct target *target, uint32_t op1,
-               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+               uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
 {
        struct arm *arm = target->arch_info;
        struct arm7_9_common *arm7_9 = arm->arch_info;
@@ -410,7 +410,7 @@ static int feroceon_write_cp15(struct target *target, uint32_t op1,
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, crn, crm, op2), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
        return arm7_9_execute_sys_speed(target);
 }
@@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target,
 
        /* set up target address in r0 */
        buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
-       arm->core_cache->reg_list[0].valid = 1;
-       arm->core_cache->reg_list[0].dirty = 1;
+       arm->core_cache->reg_list[0].valid = true;
+       arm->core_cache->reg_list[0].dirty = true;
        arm->core_state = ARM_STATE_ARM;
 
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
@@ -575,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target,
        /* restore target state */
        for (i = 0; i <= 5; i++) {
                buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
-               arm->core_cache->reg_list[i].valid = 1;
-               arm->core_cache->reg_list[i].dirty = 1;
+               arm->core_cache->reg_list[i].valid = true;
+               arm->core_cache->reg_list[i].dirty = true;
        }
        buf_set_u32(arm->pc->value, 0, 32, save[i]);
-       arm->pc->valid = 1;
-       arm->pc->dirty = 1;
+       arm->pc->valid = true;
+       arm->pc->dirty = true;
        arm->core_state = core_state;
 
        return retval;
@@ -593,6 +593,11 @@ static int feroceon_init_target(struct command_context *cmd_ctx,
        return ERROR_OK;
 }
 
+static void feroceon_deinit_target(struct target *target)
+{
+       arm9tdmi_deinit_target(target);
+}
+
 static void feroceon_common_setup(struct target *target)
 {
        struct arm *arm = target->arch_info;
@@ -729,6 +734,7 @@ struct target_type feroceon_target = {
        .commands = arm926ejs_command_handlers,
        .target_create = feroceon_target_create,
        .init_target = feroceon_init_target,
+       .deinit_target = feroceon_deinit_target,
        .examine = feroceon_examine,
 };