dsp5680xx - mark erase after unlocking flash

[fw/openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 133ad4f66ce9b55a498128dca8ab908e1b460738..9bd45bedf71cd7400000599e67be75e5b78a7efa 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -59,7 +59,7 @@
 #include "arm_opcodes.h"
 
 
-int feroceon_assert_reset(struct target *target)
+static int feroceon_assert_reset(struct target *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -72,22 +72,26 @@ int feroceon_assert_reset(struct target *target)
        return arm7_9_assert_reset(target);
 }
 
-int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
+static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 {
        struct scan_field fields[3];
        uint8_t out_buf[4];
        uint8_t instr_buf[4];
        uint8_t sysspeed_buf = 0x0;
+       int retval;
 
        /* prepare buffer */
        buf_set_u32(out_buf, 0, 32, 0);
 
        buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-       jtag_set_end_state(TAP_DRPAUSE);
-       arm_jtag_scann(jtag_info, 0x1);
+       retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+       if (retval != ERROR_OK)
+               return retval;
 
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = out_buf;
@@ -101,14 +105,15 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
        fields[2].out_value = instr_buf;
        fields[2].in_value = NULL;
 
-       jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
-       /* no jtag_add_runtest(0, jtag_get_end_state()) here */
+       /* no jtag_add_runtest(0, TAP_DRPAUSE) here */
 
        return ERROR_OK;
 }
 
-void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
+static void feroceon_change_to_arm(struct target *target, uint32_t *r0,
+               uint32_t *pc)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -154,7 +159,8 @@ void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
        *pc -= (12 + 4);
 }
 
-void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16])
+static void feroceon_read_core_regs(struct target *target,
+               uint32_t mask, uint32_t* core_regs[16])
 {
        int i;
        struct arm *armv4_5 = target->arch_info;
@@ -173,7 +179,8 @@ void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* cor
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size)
+static void feroceon_read_core_regs_target_buffer(struct target *target,
+               uint32_t mask, void* buffer, int size)
 {
        int i;
        struct arm *armv4_5 = target->arch_info;
@@ -210,7 +217,7 @@ void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask,
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
+static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -233,7 +240,7 @@ void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
+static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -274,7 +281,8 @@ void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
+static void feroceon_write_xpsr_im8(struct target *target,
+               uint8_t xpsr_im, int rot, int spsr)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -291,7 +299,8 @@ void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, in
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
+static void feroceon_write_core_regs(struct target *target,
+               uint32_t mask, uint32_t core_regs[16])
 {
        int i;
        struct arm *armv4_5 = target->arch_info;
@@ -311,7 +320,7 @@ void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t cor
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_branch_resume(struct target *target)
+static void feroceon_branch_resume(struct target *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -326,7 +335,7 @@ void feroceon_branch_resume(struct target *target)
        arm7_9->need_bypass_before_restart = 1;
 }
 
-void feroceon_branch_resume_thumb(struct target *target)
+static void feroceon_branch_resume_thumb(struct target *target)
 {
        LOG_DEBUG("-");
 
@@ -361,7 +370,8 @@ void feroceon_branch_resume_thumb(struct target *target)
        arm7_9->need_bypass_before_restart = 1;
 }
 
-int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int feroceon_read_cp15(struct target *target, uint32_t op1,
+               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -383,7 +393,8 @@ int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32
        return jtag_execute_queue();
 }
 
-int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int feroceon_write_cp15(struct target *target, uint32_t op1,
+               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -402,7 +413,7 @@ int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint3
        return arm7_9_execute_sys_speed(target);
 }
 
-void feroceon_set_dbgrq(struct target *target)
+static void feroceon_set_dbgrq(struct target *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -412,7 +423,7 @@ void feroceon_set_dbgrq(struct target *target)
        embeddedice_store_reg(dbg_ctrl);
 }
 
-void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
+static void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -425,7 +436,7 @@ void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 }
 
-void feroceon_disable_single_step(struct target *target)
+static void feroceon_disable_single_step(struct target *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -437,7 +448,7 @@ void feroceon_disable_single_step(struct target *target)
        embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 }
 
-int feroceon_examine_debug_reason(struct target *target)
+static int feroceon_examine_debug_reason(struct target *target)
 {
        /* the MOE is not implemented */
        if (target->debug_reason != DBG_REASON_SINGLESTEP)
@@ -448,7 +459,8 @@ int feroceon_examine_debug_reason(struct target *target)
        return ERROR_OK;
 }
 
-int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+static int feroceon_bulk_write_memory(struct target *target,
+               uint32_t address, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm *armv4_5 = target->arch_info;
@@ -577,13 +589,14 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
        return retval;
 }
 
-int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
+static int feroceon_init_target(struct command_context *cmd_ctx,
+               struct target *target)
 {
        arm9tdmi_init_target(cmd_ctx, target);
        return ERROR_OK;
 }
 
-void feroceon_common_setup(struct target *target)
+static void feroceon_common_setup(struct target *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -616,7 +629,7 @@ void feroceon_common_setup(struct target *target)
        arm7_9->wp1_used_default = -1;
 }
 
-int feroceon_target_create(struct target *target, Jim_Interp *interp)
+static int feroceon_target_create(struct target *target, Jim_Interp *interp)
 {
        struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
 
@@ -630,7 +643,7 @@ int feroceon_target_create(struct target *target, Jim_Interp *interp)
        return ERROR_OK;
 }
 
-int dragonite_target_create(struct target *target, Jim_Interp *interp)
+static int dragonite_target_create(struct target *target, Jim_Interp *interp)
 {
        struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
 
@@ -640,7 +653,7 @@ int dragonite_target_create(struct target *target, Jim_Interp *interp)
        return ERROR_OK;
 }
 
-int feroceon_examine(struct target *target)
+static int feroceon_examine(struct target *target)
 {
        struct arm *armv4_5;
        struct arm7_9_common *arm7_9;