target_type_t -> struct target_type

[fw/openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 0439f813d2e756e2a009f88a1e9cb61f6cd19472..73292e1077d9105ec9a2bc90a9d73ec7e1b002d3 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -58,7 +58,7 @@
 
 int feroceon_assert_reset(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        int ud = arm7_9->use_dbgrq;
 
@@ -110,7 +110,7 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 
 void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -157,7 +157,7 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -176,7 +176,7 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg
 void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
@@ -212,7 +212,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void
 
 void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -235,7 +235,7 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 
 void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -276,7 +276,7 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 
 void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -294,7 +294,7 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps
 void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -313,7 +313,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg
 
 void feroceon_branch_resume(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -330,7 +330,7 @@ void feroceon_branch_resume_thumb(target_t *target)
 {
        LOG_DEBUG("-");
 
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
@@ -363,7 +363,7 @@ void feroceon_branch_resume_thumb(target_t *target)
 
 int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int err;
@@ -385,7 +385,7 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR
 
 int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
@@ -404,7 +404,7 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 
 void feroceon_set_dbgrq(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
@@ -414,7 +414,7 @@ void feroceon_set_dbgrq(target_t *target)
 
 void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        /* set a breakpoint there */
@@ -427,7 +427,7 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 
 void feroceon_disable_single_step(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
@@ -451,7 +451,7 @@ int feroceon_examine_debug_reason(target_t *target)
 int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        int retval;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        enum armv4_5_state core_state = armv4_5->core_state;
        uint32_t x, flip, shift, save[7];
@@ -585,7 +585,7 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
 
 void feroceon_common_setup(struct target_s *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        /* override some insn sequence functions */
@@ -642,7 +642,7 @@ int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
 
 int feroceon_examine(struct target_s *target)
 {
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
        int retval;
 
@@ -674,7 +674,7 @@ int feroceon_examine(struct target_s *target)
        return ERROR_OK;
 }
 
-target_type_t feroceon_target =
+struct target_type feroceon_target =
 {
        .name = "feroceon",
 
@@ -712,7 +712,7 @@ target_type_t feroceon_target =
        .examine = feroceon_examine,
 };
 
-target_type_t dragonite_target =
+struct target_type dragonite_target =
 {
        .name = "dragonite",