flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / src / target / etm.h

diff --git a/src/target/etm.h b/src/target/etm.h
index 4224de675b9ad58fab41cfb0b8acd789a2bf47a5..be5f2c7d07de8ccef6887284ec5190d34427ac9c 100644 (file)
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -1,27 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
  *   Copyright (C) 2007 by Vincent Palatin                                 *
  *   vincent.palatin_openocd@m4x.org                                       *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
-#ifndef ETM_H
-#define ETM_H
+
+#ifndef OPENOCD_TARGET_ETM_H
+#define OPENOCD_TARGET_ETM_H
 
 #include "trace.h"
 #include "arm_jtag.h"
@@ -29,8 +17,7 @@
 struct image;
 
 /* ETM registers (JTAG protocol) */
-enum
-{
+enum {
        ETM_CTRL = 0x00,
        ETM_CONFIG = 0x01,
        ETM_TRIG_EVENT = 0x02,
@@ -71,9 +58,8 @@ enum
        ETM_ID = 0x79,
 };
 
-struct etm_reg
-{
-       uint32_t value;
+struct etm_reg {
+       uint8_t value[4];
        const struct etm_reg_info *reg_info;
        struct arm_jtag *jtag_info;
 };
@@ -84,8 +70,7 @@ struct etm_reg
  *
  * NOTE that these have evolved since the ~v1.3 defns ...
  */
-enum
-{
+enum {
        ETM_CTRL_POWERDOWN      = (1 << 0),
        ETM_CTRL_MONITOR_CPRT   = (1 << 1),
 
@@ -118,7 +103,7 @@ enum
        ETM_PORT_HALF_CLOCK     = (1 << 13),
        ETM_PORT_CLOCK_MASK     = (1 << 13),
 
-       // bits 15:14 == context ID size used in tracing
+       /* bits 15:14 == context ID size used in tracing */
        ETM_CTRL_CONTEXTID_NONE = (0 << 14),
        ETM_CTRL_CONTEXTID_8    = (1 << 14),
        ETM_CTRL_CONTEXTID_16   = (2 << 14),
@@ -131,14 +116,13 @@ enum
        ETM_PORT_DEMUXED        = (2 << 16),
        ETM_PORT_MODE_MASK      = (3 << 16),
 
-       // bits 31:18 defined in v3.0 and later (e.g. ARM11+)
+       /* bits 31:18 defined in v3.0 and later (e.g. ARM11+) */
 };
 
 /* forward-declare ETM context */
 struct etm_context;
 
-struct etm_capture_driver
-{
+struct etm_capture_driver {
        const char *name;
        const struct command_registration *commands;
        int (*init)(struct etm_context *etm_ctx);
@@ -148,14 +132,12 @@ struct etm_capture_driver
        int (*stop_capture)(struct etm_context *etm_ctx);
 };
 
-enum
-{
+enum {
        ETMV1_TRACESYNC_CYCLE = 0x1,
        ETMV1_TRIGGER_CYCLE = 0x2,
 };
 
-struct etmv1_trace_data
-{
+struct etmv1_trace_data {
        uint8_t pipestat;       /* bits 0-2 pipeline status */
        uint16_t packet;                /* packet data (4, 8 or 16 bit) */
        int flags;              /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
@@ -166,8 +148,7 @@ struct etmv1_trace_data
  * this will have to be split into version independent elements
  * and a version specific part
  */
-struct etm_context
-{
+struct etm_context {
        struct target *target;          /* target this ETM is connected to */
        struct reg_cache *reg_cache;            /* ETM register cache */
        struct etm_capture_driver *capture_driver;      /* driver used to access ETM data */
@@ -194,8 +175,7 @@ struct etm_context
 };
 
 /* PIPESTAT values */
-typedef enum
-{
+typedef enum {
        STAT_IE = 0x0,
        STAT_ID = 0x1,
        STAT_IN = 0x2,
@@ -207,19 +187,18 @@ typedef enum
 } etmv1_pipestat_t;
 
 /* branch reason values */
-typedef enum
-{
+typedef enum {
        BR_NORMAL  = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
        BR_ENABLE  = 0x1, /* Trace has been enabled */
        BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
        BR_NODEBUG = 0x3, /* ARM has exited for debug state */
-       BR_PERIOD  = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
+       BR_PERIOD  = 0x4, /* Periodic synchronization point (ETM >= v1.2)*/
        BR_RSVD5   = 0x5, /* reserved */
        BR_RSVD6   = 0x6, /* reserved */
        BR_RSVD7   = 0x7, /* reserved */
 } etmv1_branch_reason_t;
 
-struct reg_cache* etm_build_reg_cache(struct target *target,
+struct reg_cache *etm_build_reg_cache(struct target *target,
                struct arm_jtag *jtag_info, struct etm_context *etm_ctx);
 
 int etm_setup(struct target *target);
@@ -231,4 +210,4 @@ extern const struct command_registration etm_command_handlers[];
 #define ERROR_ETM_CAPTURE_INIT_FAILED  (-1302)
 #define ERROR_ETM_ANALYSIS_FAILED      (-1303)
 
-#endif /* ETM_H */
+#endif /* OPENOCD_TARGET_ETM_H */