#include "config.h"
#endif
-#include <string.h>
-
#include "etm.h"
#include "etb.h"
-
-#include "armv4_5.h"
+#include "image.h"
#include "arm7_9_common.h"
#include "arm_disassembler.h"
-#include "arm_simulator.h"
-#include "log.h"
-#include "arm_jtag.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
-#include "fileio.h"
-
-#include <stdlib.h>
/* ETM register access functionality
*
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
etm_context_t *etm_ctx = arm7_9->etm_ctx;
reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+
/* initialize some ETM control register settings */
etm_get_reg(etm_ctrl_reg);
etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
int etm_get_reg(reg_t *reg)
{
int retval;
+
if ((retval = etm_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
return ERROR_OK;
}
-int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
{
etm_reg_t *etm_reg = reg->arch_info;
- u8 reg_addr = etm_reg->addr & 0x7f;
+ uint8_t reg_addr = etm_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i", etm_reg->addr);
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
+ fields[0].check_value = NULL;
+ fields[0].check_mask = NULL;
fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
+ fields[1].check_value = NULL;
+ fields[1].check_mask = NULL;
fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
+ fields[2].check_value = NULL;
+ fields[2].check_mask = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
fields[0].in_value = reg->value;
- jtag_set_check_value(fields+0, check_value, check_mask, NULL);
+ fields[0].check_value = check_value;
+ fields[0].check_mask = check_mask;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
free(fields[1].out_value);
free(fields[2].out_value);
int etm_set_reg(reg_t *reg, u32 value)
{
int retval;
+
if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
return ERROR_OK;
}
-int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
+int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
{
int retval;
+
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if ((retval = jtag_execute_queue()) != ERROR_OK)
int etm_write_reg(reg_t *reg, u32 value)
{
etm_reg_t *etm_reg = reg->arch_info;
- u8 reg_addr = etm_reg->addr & 0x7f;
+ uint8_t reg_addr = etm_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
- fields[0].out_value = malloc(4);
+ uint8_t tmp1[4];
+ fields[0].out_value = tmp1;
buf_set_u32(fields[0].out_value, 0, 32, value);
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
+ uint8_t tmp2;
+ fields[1].out_value = &tmp2;
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
+ uint8_t tmp3;
+ fields[2].out_value = &tmp3;
buf_set_u32(fields[2].out_value, 0, 1, 1);
- fields[2].out_mask = NULL;
fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, TAP_INVALID);
- free(fields[0].out_value);
- free(fields[1].out_value);
- free(fields[2].out_value);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
return ERROR_OK;
}
if (ctx->core_state == ARMV4_5_STATE_ARM)
{
- u8 buf[4];
+ uint8_t buf[4];
if ((retval = image_read_section(ctx->image, section,
ctx->current_pc - ctx->image->sections[section].base_address,
4, buf, &size_read)) != ERROR_OK)
}
else if (ctx->core_state == ARMV4_5_STATE_THUMB)
{
- u8 buf[2];
+ uint8_t buf[2];
if ((retval = image_read_section(ctx->image, section,
ctx->current_pc - ctx->image->sections[section].base_address,
2, buf, &size_read)) != ERROR_OK)
return ERROR_OK;
}
-static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
+static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
{
while (ctx->data_index < ctx->trace_depth)
{
static int etmv1_branch_address(etm_context_t *ctx)
{
int retval;
- u8 packet;
+ uint8_t packet;
int shift = 0;
int apo;
u32 i;
static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
{
int j;
- u8 buf[4];
+ uint8_t buf[4];
int retval;
for (j = 0; j < size; j++)
while (ctx->pipe_index < ctx->trace_depth)
{
- u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
+ uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
u32 next_pc = ctx->current_pc;
u32 old_data_index = ctx->data_index;
u32 old_data_half = ctx->data_half;
if (ctx->tracemode & ETMV1_TRACE_ADDR)
{
- u8 packet;
+ uint8_t packet;
int shift = 0;
do {
{
if (((instruction.type == ARM_B) ||
(instruction.type == ARM_BL) ||
- (instruction.type == ARM_BLX)) &&
+ (instruction.type == ARM_BLX)) &&
(instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
{
next_pc = instruction.info.b_bl_bx_blx.target_address;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target = get_target_by_num(strtoul(args[0], NULL, 0));
-
+ target = get_target(args[0]);
if (!target)
{
- LOG_ERROR("target number '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
fileio_read_u32(&file, &etm_ctx->trace_depth);
etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
- if(etm_ctx->trace_data == NULL)
+ if (etm_ctx->trace_data == NULL)
{
command_print(cmd_ctx, "not enough memory to perform operation");
fileio_close(&file);
if ((new_value < 2) || (new_value > 100))
{
- command_print(cmd_ctx, "valid settings are 2% to 100%");
+ command_print(cmd_ctx, "valid settings are 2%% to 100%%");
}
else
{
if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
{
- switch(retval)
+ switch (retval)
{
case ERROR_ETM_ANALYSIS_FAILED:
command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
{
etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
- register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
+ register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
+ COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
return ERROR_OK;
}
int etm_register_user_commands(struct command_context_s *cmd_ctx)
{
register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
- COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
+ COMMAND_EXEC, "configure trace mode <none|data|address|all> "
+ "<context_id_bits> <cycle_accurate> <branch_output>");
register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
COMMAND_EXEC, "display info about the current target's ETM");
- register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
+ register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
COMMAND_EXEC, "display current target's ETM status");
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