if (!etb)
{
LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
+ for (i = 0; i < num_regs; i++)
+ {
+ free(reg_list[i].value);
+ }
+ free(reg_cache);
+ free(arch_info);
return ERROR_OK;
}
int etm_setup(target_t *target)
{
int retval;
- u32 etm_ctrl_value;
+ uint32_t etm_ctrl_value;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
etm_context_t *etm_ctx = arm7_9->etm_ctx;
buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
+ if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
{
LOG_ERROR("ETM capture driver initialization failed");
return retval;
return etm_read_reg_w_check(reg, NULL, NULL);
}
-int etm_set_reg(reg_t *reg, u32 value)
+int etm_set_reg(reg_t *reg, uint32_t value)
{
int retval;
return ERROR_OK;
}
-int etm_write_reg(reg_t *reg, u32 value)
+int etm_write_reg(reg_t *reg, uint32_t value)
{
etm_reg_t *etm_reg = reg->arch_info;
uint8_t reg_addr = etm_reg->addr & 0x7f;
scan_field_t fields[3];
- LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
+ LOG_DEBUG("%i: 0x%8.8" PRIx32 "", etm_reg->addr, value);
jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
{
int i;
int section = -1;
- u32 size_read;
- u32 opcode;
+ uint32_t size_read;
+ uint32_t opcode;
int retval;
if (!ctx->image)
uint8_t packet;
int shift = 0;
int apo;
- u32 i;
+ uint32_t i;
/* quit analysis if less than two cycles are left in the trace
* because we can't extract the APO */
return 0;
}
-static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
+static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
{
int j;
uint8_t buf[4];
while (ctx->pipe_index < ctx->trace_depth)
{
uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
- u32 next_pc = ctx->current_pc;
- u32 old_data_index = ctx->data_index;
- u32 old_data_half = ctx->data_half;
- u32 old_index = ctx->pipe_index;
- u32 last_instruction = ctx->last_instruction;
- u32 cycles = 0;
+ uint32_t next_pc = ctx->current_pc;
+ uint32_t old_data_index = ctx->data_index;
+ uint32_t old_data_half = ctx->data_half;
+ uint32_t old_index = ctx->pipe_index;
+ uint32_t last_instruction = ctx->last_instruction;
+ uint32_t cycles = 0;
int current_pc_ok = ctx->pc_ok;
if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
next_pc = ctx->last_branch;
break;
case 0x1: /* tracing enabled */
- command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
+ command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
break;
case 0x2: /* trace restarted after FIFO overflow */
- command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
+ command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
break;
case 0x3: /* exit from debug state */
- command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
+ command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
*/
if (!current_pc_ok)
{
- command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
+ command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
ctx->current_pc = next_pc;
ctx->pipe_index++;
continue;
}
break;
default: /* reserved */
- LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
+ LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
exit(-1);
break;
}
}
else
{
- command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
+ command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
{
- u32 new_data_index = ctx->data_index;
- u32 new_data_half = ctx->data_half;
+ uint32_t new_data_index = ctx->data_index;
+ uint32_t new_data_half = ctx->data_half;
/* in case of a branch with data, the branch target address was consumed before
* we temporarily go back to the saved data index */
if (ctx->ptr_ok)
{
- command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
+ command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
}
}
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- u32 data;
+ uint32_t data;
if (etmv1_data(ctx, 4, &data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
- command_print(cmd_ctx, "data: 0x%8.8x", data);
+ command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
}
}
}
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
{
- u32 data;
+ uint32_t data;
if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
- command_print(cmd_ctx, "data: 0x%8.8x", data);
+ command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
}
}
if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
{
snprintf(cycles_text, 32, " (%i %s)",
- cycles,
+ (int)cycles,
(cycles == 1) ? "cycle" : "cycles");
}
}
else if (argc != 0)
{
- command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
+ command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
return ERROR_OK;
}
if (argc != 5)
{
+ free(etm_ctx);
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (!target)
{
LOG_ERROR("target '%s' not defined", args[0]);
+ free(etm_ctx);
return ERROR_FAIL;
}
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
+ free(etm_ctx);
return ERROR_FAIL;
}
break;
default:
command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
+ free(etm_ctx);
return ERROR_FAIL;
}
else
{
command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
+ free(etm_ctx);
return ERROR_FAIL;
}
else
{
command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
+ free(etm_ctx);
return ERROR_FAIL;
}
- for (i=0; etm_capture_drivers[i]; i++)
+ for (i = 0; etm_capture_drivers[i]; i++)
{
if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
{
int retval;
- if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
+ if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
free(etm_ctx);
return retval;
etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
etm_get_reg(etm_config_reg);
- command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
- command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
- command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
- command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
+ command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
+ command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4));
+ command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5));
+ command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3));
command_print(cmd_ctx, "sequencer %spresent",
(buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
- command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
- command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
+ command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3));
+ command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3));
command_print(cmd_ctx, "FIFO full %spresent",
(buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
- command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
+ command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3));
etm_get_reg(etm_sys_config_reg);
if (arm7_9->etm_ctx->trace_depth > 0)
{
- command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
+ command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
}
}
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
etm_context_t *etm_ctx;
- u32 i;
+ uint32_t i;
if (argc != 1)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
etm_context_t *etm_ctx;
- u32 i;
+ uint32_t i;
if (argc != 1)
{
etm_ctx->trace_data = NULL;
}
- fileio_read_u32(&file, &etm_ctx->capture_status);
- fileio_read_u32(&file, &etm_ctx->portmode);
- fileio_read_u32(&file, &etm_ctx->tracemode);
- fileio_read_u32(&file, &etm_ctx->trace_depth);
-
+ {
+ uint32_t tmp;
+ fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
+ fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
+ fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
+ fileio_read_u32(&file, &etm_ctx->trace_depth);
+ }
etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
if (etm_ctx->trace_data == NULL)
{
for (i = 0; i < etm_ctx->trace_depth; i++)
{
- u32 pipestat, packet, flags;
+ uint32_t pipestat, packet, flags;
fileio_read_u32(&file, &pipestat);
fileio_read_u32(&file, &packet);
fileio_read_u32(&file, &flags);
if (argc > 0)
{
- u32 new_value = strtoul(args[0], NULL, 0);
+ uint32_t new_value = strtoul(args[0], NULL, 0);
if ((new_value < 2) || (new_value > 100))
{
}
}
- command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
+ command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
return ERROR_OK;
}
int etm_register_user_commands(struct command_context_s *cmd_ctx)
{
register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
- COMMAND_EXEC, "configure trace mode <none|data|address|all> "
+ COMMAND_EXEC, "configure trace mode <none | data | address | all> "
"<context_id_bits> <cycle_accurate> <branch_output>");
register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
projects / fw / openocd / blobdiff