static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-static int etb_set_instr(etb_t *etb, u32 new_instr)
+static int etb_set_instr(etb_t *etb, uint32_t new_instr)
{
jtag_tap_t *tap;
tap = etb->tap;
- if (tap==NULL)
+ if (tap == NULL)
return ERROR_FAIL;
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
field.in_value = NULL;
- jtag_add_ir_scan(1, &field, TAP_INVALID);
+ jtag_add_ir_scan(1, &field, jtag_get_end_state());
free(field.out_value);
}
return ERROR_OK;
}
-static int etb_scann(etb_t *etb, u32 new_scan_chain)
+static int etb_scann(etb_t *etb, uint32_t new_scan_chain)
{
if (etb->cur_scan_chain != new_scan_chain)
{
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
- jtag_add_dr_scan(1, &field, TAP_INVALID);
+ jtag_add_dr_scan(1, &field, jtag_get_end_state());
etb->cur_scan_chain = new_scan_chain;
return ERROR_OK;
}
+static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *);
+static int etb_set_reg_w_exec(reg_t *, uint8_t *);
+
+static int etb_read_reg(reg_t *reg)
+{
+ return etb_read_reg_w_check(reg, NULL, NULL);
+}
+
+static int etb_get_reg(reg_t *reg)
+{
+ int retval;
+
+ if ((retval = etb_read_reg(reg)) != ERROR_OK)
+ {
+ LOG_ERROR("BUG: error scheduling etm register read");
+ return retval;
+ }
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ LOG_ERROR("register read failed");
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
reg_cache_t* etb_build_reg_cache(etb_t *etb)
{
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
return reg_cache;
}
-static int etb_get_reg(reg_t *reg)
+static void etb_getbuf(jtag_callback_data_t arg)
{
- int retval;
-
- if ((retval = etb_read_reg(reg)) != ERROR_OK)
- {
- LOG_ERROR("BUG: error scheduling etm register read");
- return retval;
- }
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_ERROR("register read failed");
- return retval;
- }
+ uint8_t *in = (uint8_t *)arg;
- return ERROR_OK;
+ *((uint32_t *)in) = buf_get_u32(in, 0, 32);
}
-static void etb_getbuf(u8 *in)
-{
- *((u32 *)in)=buf_get_u32(in, 0, 32);
-}
-
-
-static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
+static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames)
{
scan_field_t fields[3];
int i;
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
-
+
fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
for (i = 0; i < num_frames; i++)
{
else
buf_set_u32(fields[1].out_value, 0, 7, 0);
- fields[0].in_value = (u8 *)(data+i);
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ fields[0].in_value = (uint8_t *)(data + i);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_add_callback(etb_getbuf, (u8 *)(data+i));
+ jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
}
jtag_execute_queue();
return ERROR_OK;
}
-int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+static int etb_read_reg_w_check(reg_t *reg,
+ uint8_t* check_value, uint8_t* check_mask)
{
etb_reg_t *etb_reg = reg->arch_info;
- u8 reg_addr = etb_reg->addr & 0x7f;
+ uint8_t reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
- LOG_DEBUG("%i", etb_reg->addr);
+ LOG_DEBUG("%i", (int)(etb_reg->addr));
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
+ fields[0].check_value = NULL;
+ fields[0].check_mask = NULL;
fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_value = NULL;
+ fields[1].check_value = NULL;
+ fields[1].check_mask = NULL;
fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
+ fields[2].check_value = NULL;
+ fields[2].check_mask = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
*/
buf_set_u32(fields[1].out_value, 0, 7, 0x0);
fields[0].in_value = reg->value;
+ fields[0].check_value = check_value;
+ fields[0].check_mask = check_mask;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
-
- jtag_check_value_mask(fields+0, check_value, check_mask);
+ jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
-int etb_read_reg(reg_t *reg)
-{
- return etb_read_reg_w_check(reg, NULL, NULL);
-}
+static int etb_write_reg(reg_t *, uint32_t);
-int etb_set_reg(reg_t *reg, u32 value)
+static int etb_set_reg(reg_t *reg, uint32_t value)
{
int retval;
return ERROR_OK;
}
-int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
+static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
{
int retval;
return ERROR_OK;
}
-int etb_write_reg(reg_t *reg, u32 value)
+static int etb_write_reg(reg_t *reg, uint32_t value)
{
etb_reg_t *etb_reg = reg->arch_info;
- u8 reg_addr = etb_reg->addr & 0x7f;
+ uint8_t reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
- LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
+ LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
return ERROR_OK;
}
-int etb_store_reg(reg_t *reg)
-{
- return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
-
static int etb_register_commands(struct command_context_s *cmd_ctx)
{
command_t *etb_cmd;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target = get_target_by_num(strtoul(args[0], NULL, 0));
+ target = get_target(args[0]);
if (!target)
{
- LOG_ERROR("target number '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
return ERROR_FAIL;
}
- tap = jtag_TapByString( args[1] );
+ tap = jtag_tap_by_string(args[1]);
if (tap == NULL)
{
- command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
+ command_print(cmd_ctx, "Tap: %s does not exist", args[1]);
return ERROR_FAIL;
}
if (etb_timeout == 0)
{
- LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
+ LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "",
buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
}
etb_t *etb = etm_ctx->capture_driver_priv;
int first_frame = 0;
int num_frames = etb->ram_depth;
- u32 *trace_data = NULL;
+ uint32_t *trace_data = NULL;
int i, j;
etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
/* read data into temporary array for unpacking */
- trace_data = malloc(sizeof(u32) * num_frames);
+ trace_data = malloc(sizeof(uint32_t) * num_frames);
etb_read_ram(etb, trace_data, num_frames);
if (etm_ctx->trace_depth > 0)
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
- /* trace word j+1 */
- etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
- etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
- etm_ctx->trace_data[j+1].flags = 0;
+ /* trace word j + 1 */
+ etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
+ etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
+ etm_ctx->trace_data[j + 1].flags = 0;
if ((trace_data[i] & 0x8000) >> 15)
{
- etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
}
- if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
{
- etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
- etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+ etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
}
- /* trace word j+2 */
- etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
- etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
- etm_ctx->trace_data[j+2].flags = 0;
+ /* trace word j + 2 */
+ etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
+ etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
+ etm_ctx->trace_data[j + 2].flags = 0;
if ((trace_data[i] & 0x800000) >> 23)
{
- etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
+ etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
}
- if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
+ if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
{
- etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
- etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
+ etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
+ etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 3;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
- /* trace word j+1 */
- etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
- etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
- etm_ctx->trace_data[j+1].flags = 0;
+ /* trace word j + 1 */
+ etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
+ etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
+ etm_ctx->trace_data[j + 1].flags = 0;
if ((trace_data[i] & 0x800000) >> 23)
{
- etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
}
- if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
{
- etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
- etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+ etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 2;
static int etb_start_capture(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
- u32 etb_ctrl_value = 0x1;
- u32 trigger_count;
+ uint32_t etb_ctrl_value = 0x1;
+ uint32_t trigger_count;
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
{
projects / fw / openocd / blobdiff