flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / src / target / esirisc.h

diff --git a/src/target/esirisc.h b/src/target/esirisc.h
index 57deba616732842c9e2f443e503495aee7667018..7496b1eda7a51ffab7d3a30761860bb7e6b3311b 100644 (file)
--- a/src/target/esirisc.h
+++ b/src/target/esirisc.h
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2018 by Square, Inc.                                    *
  *   Steven Stallion <stallion@squareup.com>                               *
  *   James Zhao <hjz@squareup.com>                                         *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifndef OPENOCD_TARGET_ESIRISC_H
@@ -47,7 +36,7 @@
 #define EID_SYSTEM_CALL                        0x0b
 #define EID_MEMORY_MANAGEMENT  0x0c
 #define EID_UNRECOVERABLE              0x0d
-#define EID_INTERRUPTn                 0x20
+#define EID_INTERRUPT_N                        0x20
 
 /* Exception Entry Points */
 #define ENTRY_RESET                            0x00
@@ -58,7 +47,7 @@
 #define ENTRY_SYSCALL                  0x05
 #define ENTRY_DEBUG                            0x06
 #define ENTRY_NMI                              0x07
-#define ENTRY_INTERRUPTn               0x08
+#define ENTRY_INTERRUPT_N              0x08
 
 /* Hardware Debug Control */
 #define HWDC_R                                 (1<<4)  /* Reset & Hardware Failure */