* Copyright (C) 2005, 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifndef EMBEDDED_ICE_H
#define EMBEDDED_ICE_H
-#include "target.h"
-#include "register.h"
-#include "arm_jtag.h"
#include "arm7_9_common.h"
-enum
-{
+enum {
EICE_DBG_CTRL = 0,
EICE_DBG_STAT = 1,
EICE_COMMS_CTRL = 2,
EICE_VEC_CATCH = 16
};
-enum
-{
+enum {
EICE_DBG_CONTROL_ICEDIS = 5,
- EICE_DBG_CONTROL_MONEN = 4,
+ EICE_DBG_CONTROL_MONEN = 4,
EICE_DBG_CONTROL_INTDIS = 2,
EICE_DBG_CONTROL_DBGRQ = 1,
EICE_DBG_CONTROL_DBGACK = 0,
};
-enum
-{
+enum {
EICE_DBG_STATUS_IJBIT = 5,
EICE_DBG_STATUS_ITBIT = 4,
EICE_DBG_STATUS_SYSCOMP = 3,
EICE_DBG_STATUS_DBGACK = 0
};
-enum
-{
+enum {
EICE_W_CTRL_ENABLE = 0x100,
EICE_W_CTRL_RANGE = 0x80,
EICE_W_CTRL_CHAIN = 0x40,
EICE_W_CTRL_nRW = 0x1
};
-enum
-{
+enum {
EICE_COMM_CTRL_WBIT = 1,
EICE_COMM_CTRL_RBIT = 0
};
-typedef struct embeddedice_reg_s
-{
+struct embeddedice_reg {
int addr;
- arm_jtag_t *jtag_info;
-} embeddedice_reg_t;
-
-extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
-extern int embeddedice_read_reg(reg_t *reg);
-extern int embeddedice_write_reg(reg_t *reg, u32 value);
-extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
-extern int embeddedice_store_reg(reg_t *reg);
-extern int embeddedice_set_reg(reg_t *reg, u32 value);
-extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
-extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
-extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
-extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
-
-/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
- * embeddedice_write_reg
+ struct arm_jtag *jtag_info;
+};
+
+struct reg_cache *embeddedice_build_reg_cache(struct target *target,
+ struct arm7_9_common *arm7_9);
+
+int embeddedice_setup(struct target *target);
+
+int embeddedice_read_reg(struct reg *reg);
+int embeddedice_read_reg_w_check(struct reg *reg,
+ uint8_t *check_value, uint8_t *check_mask);
+
+void embeddedice_write_reg(struct reg *reg, uint32_t value);
+void embeddedice_store_reg(struct reg *reg);
+
+void embeddedice_set_reg(struct reg *reg, uint32_t value);
+
+int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
+int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
+
+int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
+
+/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be
+ * this faster version of embeddedice_write_reg
*/
-static __inline void embeddedice_write_reg_inner(reg_t *reg, u32 value)
+static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)
{
- embeddedice_reg_t *ice_reg = reg->arch_info;
- u8 reg_addr = ice_reg->addr & 0x1f;
- jtag_add_shift(TAP_SD, TAP_PD, 32, value);
- jtag_add_shift(TAP_SD, TAP_PD, 5, reg_addr);
- jtag_add_shift(TAP_SD, TAP_RTI, 1, 1);
+ static const int embeddedice_num_bits[] = {32, 6};
+ uint32_t values[2];
+
+ values[0] = value;
+ values[1] = (1 << 5) | reg_addr;
+
+ jtag_add_dr_out(tap, 2, embeddedice_num_bits, values, TAP_IDLE);
}
+void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer,
+ int little, int count);
#endif /* EMBEDDED_ICE_H */