MIPS: fastdata bulk write fallback

[fw/openocd] / src / target / embeddedice.c

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 292504beb032aea0f4d0695a0796b040a7b36c95..a705d7dd15f911567d3fc4f12ca419bf77c52827 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -28,15 +28,15 @@
 #endif
 
 #include "embeddedice.h"
-
-#define ARRAY_SIZE(x)  ((int)(sizeof(x)/sizeof((x)[0])))
+#include "register.h"
 
 /**
  * @file
  *
  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  * module found on scan chain 2 in ARM7, ARM9, and some other families
- * of ARM cores.
+ * of ARM cores.  The module is called "EmbeddedICE-RT" if it has
+ * monitor mode support.
  *
  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  * Communications Channel (DCC) used to read or write 32-bit words to
@@ -144,8 +144,6 @@ static const struct {
 };
 
 
-static int embeddedice_reg_arch_type = -1;
-
 static int embeddedice_get_reg(struct reg *reg)
 {
        int retval;
@@ -158,6 +156,11 @@ static int embeddedice_get_reg(struct reg *reg)
        return retval;
 }
 
+static const struct reg_arch_type eice_reg_type = {
+       .get = embeddedice_get_reg,
+       .set = embeddedice_set_reg_w_exec,
+};
+
 /**
  * Probe EmbeddedICE module and set up local records of its registers.
  * Different versions of the modules have different capabilities, such as
@@ -175,11 +178,6 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
        int i;
        int eice_version = 0;
 
-       /* register arch-type for EmbeddedICE registers only once */
-       if (embeddedice_reg_arch_type == -1)
-               embeddedice_reg_arch_type = register_reg_arch_type(
-                               embeddedice_get_reg, embeddedice_set_reg_w_exec);
-
        /* vector_catch isn't always present */
        if (!arm7_9->has_vector_catch)
                num_regs--;
@@ -203,7 +201,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
                reg_list[i].valid = 0;
                reg_list[i].value = calloc(1, 4);
                reg_list[i].arch_info = &arch_info[i];
-               reg_list[i].arch_type = embeddedice_reg_arch_type;
+               reg_list[i].type = &eice_reg_type;
                arch_info[i].addr = eice_regs[i].addr;
                arch_info[i].jtag_info = jtag_info;
        }
@@ -284,14 +282,17 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
                         * in some unusual bits.  Let feroceon.c validate it
                         * and do the appropriate setup itself.
                         */
-                       if (strcmp(target_get_name(target), "feroceon") == 0 ||
-                           strcmp(target_get_name(target), "dragonite") == 0)
+                       if (strcmp(target_type_name(target), "feroceon") == 0 ||
+                           strcmp(target_type_name(target), "dragonite") == 0)
                                break;
                        LOG_ERROR("unknown EmbeddedICE version "
                                "(comms ctrl: 0x%8.8" PRIx32 ")",
                                buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
        }
 
+       LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
+                       target_name(target));
+
        return reg_cache;
 }
 
@@ -352,7 +353,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        fields[1].tap = ice_reg->jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
+       fields[1].out_value[0] = reg_addr;
        fields[1].in_value = NULL;
        fields[1].check_value = NULL;
        fields[1].check_mask = NULL;
@@ -361,7 +362,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        fields[2].tap = ice_reg->jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       buf_set_u32(fields[2].out_value, 0, 1, 0);
+       fields[2].out_value[0] = 0;
        fields[2].in_value = NULL;
        fields[2].check_value = NULL;
        fields[2].check_mask = NULL;
@@ -378,7 +379,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
         * EICE_COMMS_DATA would read the register twice
         * reading the control register is safe
         */
-       buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
+       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
        /* traverse Update-DR, reading but with no other side effects */
        jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
@@ -412,13 +413,13 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
        fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       buf_set_u32(fields[2].out_value, 0, 1, 0);
+       fields[2].out_value[0] = 0;
        fields[2].in_value = NULL;
 
        jtag_add_dr_scan(3, fields, jtag_get_end_state());
@@ -429,8 +430,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
                 * to avoid reading additional data from the DCC data reg
                 */
                if (size == 1)
-                       buf_set_u32(fields[1].out_value, 0, 5,
-                                       eice_regs[EICE_COMMS_CTRL].addr);
+                       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
                fields[0].in_value = (uint8_t *)data;
                jtag_add_dr_scan(3, fields, jtag_get_end_state());
@@ -534,13 +534,13 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
        fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       buf_set_u32(fields[2].out_value, 0, 1, 1);
+       fields[2].out_value[0] = 1;
 
        fields[2].in_value = NULL;
 
@@ -590,13 +590,13 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
        fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       buf_set_u32(fields[2].out_value, 0, 1, 0);
+       fields[2].out_value[0] = 0;
        fields[2].in_value = NULL;
 
        jtag_add_dr_scan(3, fields, jtag_get_end_state());