jtag newtap change & huge manual update

[fw/openocd] / src / target / embeddedice.c

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 32e451a2eab33feae0a419c3fb38d6f75424505d..8a1b398715904da5f3659ed9f0eb444cbf36d89d 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,9 +2,12 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                      *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -83,10 +86,10 @@ char* embeddedice_reg_list[] =
 int embeddedice_reg_arch_type = -1;
 
 int embeddedice_get_reg(reg_t *reg);
-int embeddedice_set_reg(reg_t *reg, u32 value);
+void embeddedice_set_reg(reg_t *reg, u32 value);
 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
 
-int embeddedice_write_reg(reg_t *reg, u32 value);
+void embeddedice_write_reg(reg_t *reg, u32 value);
 int embeddedice_read_reg(reg_t *reg);
 
 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
@@ -219,15 +222,17 @@ int embeddedice_setup(target_t *target)
 
 int embeddedice_get_reg(reg_t *reg)
 {
-       if (embeddedice_read_reg(reg) != ERROR_OK)
+       int retval;
+       if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
        {
                LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
-               exit(-1);
+               return retval;
        }
 
-       if (jtag_execute_queue() != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                LOG_ERROR("register read failed");
+               return retval;
        }
 
        return ERROR_OK;
@@ -246,7 +251,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 
        arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 
-       fields[0].device = ice_reg->jtag_info->chain_pos;
+       fields[0].tap = ice_reg->jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = reg->value;
        fields[0].out_mask = NULL;
@@ -256,7 +261,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = ice_reg->jtag_info->chain_pos;
+       fields[1].tap = ice_reg->jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
        buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
@@ -267,7 +272,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = ice_reg->jtag_info->chain_pos;
+       fields[2].tap = ice_reg->jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -308,7 +313,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
        arm_jtag_scann(jtag_info, 0x2);
        arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-       fields[0].device = jtag_info->chain_pos;
+       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
        fields[0].out_mask = NULL;
@@ -318,7 +323,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = jtag_info->chain_pos;
+       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
@@ -329,7 +334,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = jtag_info->chain_pos;
+       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -366,34 +371,30 @@ int embeddedice_read_reg(reg_t *reg)
        return embeddedice_read_reg_w_check(reg, NULL, NULL);
 }
 
-int embeddedice_set_reg(reg_t *reg, u32 value)
+void embeddedice_set_reg(reg_t *reg, u32 value)
 {
-       if (embeddedice_write_reg(reg, value) != ERROR_OK)
-       {
-               LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
-               exit(-1);
-       }
+       embeddedice_write_reg(reg, value);
 
        buf_set_u32(reg->value, 0, reg->size, value);
        reg->valid = 1;
        reg->dirty = 0;
 
-       return ERROR_OK;
 }
 
 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 {
+       int retval;
        embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 
-       if (jtag_execute_queue() != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                LOG_ERROR("register write failed");
-               exit(-1);
+               return retval;
        }
        return ERROR_OK;
 }
 
-int embeddedice_write_reg(reg_t *reg, u32 value)
+void embeddedice_write_reg(reg_t *reg, u32 value)
 {
        embeddedice_reg_t *ice_reg = reg->arch_info;
 
@@ -405,14 +406,13 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
        arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 
        u8 reg_addr = ice_reg->addr & 0x1f;
-       embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
+       embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 
-       return ERROR_OK;
 }
 
-int embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(reg_t *reg)
 {
-       return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+       embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 }
 
 /* send <size> words of 32 bit to the DCC
@@ -430,7 +430,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
        arm_jtag_scann(jtag_info, 0x2);
        arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-       fields[0].device = jtag_info->chain_pos;
+       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = field0_out;
        fields[0].out_mask = NULL;
@@ -440,7 +440,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = jtag_info->chain_pos;
+       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
@@ -451,7 +451,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = jtag_info->chain_pos;
+       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 1);
@@ -499,7 +499,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
        arm_jtag_scann(jtag_info, 0x2);
        arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-       fields[0].device = jtag_info->chain_pos;
+       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
        fields[0].out_mask = NULL;
@@ -509,7 +509,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = jtag_info->chain_pos;
+       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
@@ -520,7 +520,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = jtag_info->chain_pos;
+       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -550,12 +550,12 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 }
 
 /* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
+void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
 {
        int i;
        for (i = 0; i < count; i++)
        {
-               embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+               embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
                buffer += 4;
        }
 }