#endif
#include "embeddedice.h"
-
-#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
+#include "register.h"
/**
* @file
*
* This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
* module found on scan chain 2 in ARM7, ARM9, and some other families
- * of ARM cores.
+ * of ARM cores. The module is called "EmbeddedICE-RT" if it has
+ * monitor mode support.
*
* EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
* Communications Channel (DCC) used to read or write 32-bit words to
};
-static int embeddedice_reg_arch_type = -1;
-
static int embeddedice_get_reg(struct reg *reg)
{
int retval;
return retval;
}
+static const struct reg_arch_type eice_reg_type = {
+ .get = embeddedice_get_reg,
+ .set = embeddedice_set_reg_w_exec,
+};
+
/**
* Probe EmbeddedICE module and set up local records of its registers.
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
struct reg_cache *
-embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
+embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
int i;
int eice_version = 0;
- /* register arch-type for EmbeddedICE registers only once */
- if (embeddedice_reg_arch_type == -1)
- embeddedice_reg_arch_type = register_reg_arch_type(
- embeddedice_get_reg, embeddedice_set_reg_w_exec);
-
/* vector_catch isn't always present */
if (!arm7_9->has_vector_catch)
num_regs--;
reg_cache->reg_list = reg_list;
reg_cache->num_regs = num_regs;
+ /* FIXME the second watchpoint unit on Feroceon and Dragonite
+ * seems not to work ... we should have a way to not set up
+ * its four registers here!
+ */
+
/* set up registers */
for (i = 0; i < num_regs; i++)
{
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
- reg_list[i].arch_type = embeddedice_reg_arch_type;
+ reg_list[i].type = &eice_reg_type;
arch_info[i].addr = eice_regs[i].addr;
arch_info[i].jtag_info = jtag_info;
}
* in some unusual bits. Let feroceon.c validate it
* and do the appropriate setup itself.
*/
- if (strcmp(target_get_name(target), "feroceon") == 0 ||
- strcmp(target_get_name(target), "dragonite") == 0)
+ if (strcmp(target_type_name(target), "feroceon") == 0 ||
+ strcmp(target_type_name(target), "dragonite") == 0)
break;
LOG_ERROR("unknown EmbeddedICE version "
"(comms ctrl: 0x%8.8" PRIx32 ")",
buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
}
+ /* On Feroceon and Dragonite the second unit is seemingly missing. */
+ LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
+ target_name(target), arm7_9->wp_available_max,
+ (arm7_9->wp_available_max != 1) ? "s" : "");
+
return reg_cache;
}
/**
* Initialize EmbeddedICE module, if needed.
*/
-int embeddedice_setup(target_t *target)
+int embeddedice_setup(struct target *target)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
/* bits 31:0 -- data (ignored here) */
- fields[0].tap = ice_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
fields[0].check_mask = NULL;
/* bits 36:32 -- register */
- fields[1].tap = ice_reg->jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
+ fields[1].out_value[0] = reg_addr;
fields[1].in_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
/* bit 37 -- 0/read */
- fields[2].tap = ice_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ fields[2].out_value[0] = 0;
fields[2].in_value = NULL;
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
/* traverse Update-DR, setting address for the next read */
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
/* bits 31:0 -- the data we're reading (and maybe checking) */
fields[0].in_value = reg->value;
* EICE_COMMS_DATA would read the register twice
* reading the control register is safe
*/
- buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
+ fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
/* traverse Update-DR, reading but with no other side effects */
- jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
return ERROR_OK;
}
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
- fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+ fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
- fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ fields[2].out_value[0] = 0;
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
while (size > 0)
{
* to avoid reading additional data from the DCC data reg
*/
if (size == 1)
- buf_set_u32(fields[1].out_value, 0, 5,
- eice_regs[EICE_COMMS_CTRL].addr);
+ fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
fields[0].in_value = (uint8_t *)data;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
data++;
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
fields[0].in_value = NULL;
- fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+ fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
- fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 1);
+ fields[2].out_value[0] = 1;
fields[2].in_value = NULL;
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
data++;
size--;
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = field0_in;
- fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+ fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
- fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ fields[2].out_value[0] = 0;
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
gettimeofday(&lap, NULL);
do {
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
projects / fw / openocd / blobdiff