adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_ap

[fw/openocd] / src / target / dsp5680xx.c

diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index a50f2cd4746b7b95169a60e296ee1437f77ae01a..d6107abc6ffa41309399e4b80f82327c4c81d7da 100644 (file)
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -93,7 +93,7 @@ static int dsp5680xx_drscan(struct target *target, uint8_t *d_in,
        if (len > 32) {
                retval = ERROR_FAIL;
                err_check(retval, DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW,
-                         "dr_len overflow, maxium is 32");
+                         "dr_len overflow, maximum is 32");
        }
        /* TODO what values of len are valid for jtag_add_plain_dr_scan? */
        /* can i send as many bits as i want? */
@@ -638,7 +638,7 @@ static int switch_tap(struct target *target, struct jtag_tap *master_tap,
  * more complicated routine, which is guaranteed to work, but requires
  * a reset. This will complicate comm with the flash module, since
  * after a reset clock divisors must be set again.
- * This implementation works most of the time, and is not accesible to the
+ * This implementation works most of the time, and is not accessible to the
  * user.
  *
  * @param target
@@ -1731,7 +1731,12 @@ static int dsp5680xx_f_ex(struct target *t, uint16_t c, uint32_t a, uint32_t d,
 }
 
 /**
- * Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.)
+ * Prior to the execution of any Flash module command, the Flash module Clock
+ * Divider (CLKDIV) register must be initialized. The values of this register
+ * determine the speed of the internal Flash Clock (FCLK). FCLK must be in the
+ * range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module.
+ * (Running FCLK too slowly wears out the module, while running it too fast
+ * under programs Flash leading to bit errors.)
  *
  * @param target
  *
@@ -1787,7 +1792,11 @@ static int set_fm_ck_div(struct target *target)
 }
 
 /**
- * Executes the FM calculate signature command. The FM will calculate over the data from @address to @address + @words -1. The result is written to a register, then read out by this function and returned in @signature. The value @signature may be compared to the the one returned by perl_crc to verify the flash was written correctly.
+ * Executes the FM calculate signature command. The FM will calculate over the
+ * data from @address to @address + @words -1. The result is written to a
+ * register, then read out by this function and returned in @signature. The
+ * value @signature may be compared to the one returned by perl_crc to
+ * verify the flash was written correctly.
  *
  * @param target
  * @param address Start of flash array where the signature should be calculated.