((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f))
/* the gdb register list is send in this order */
-static uint8_t gdb_reg_list_idx[] = {
+static const uint8_t gdb_reg_list_idx[] = {
DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0,
DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2,
DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR,
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
+ struct reg *reg_list = calloc(DSP563XX_NUMCOREREGS, sizeof(struct reg));
struct dsp563xx_core_reg *arch_info = malloc(
sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
int i;
/* conditional branch check */
if (once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg) {
if ((once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0) {
- LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)",
+ LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")",
__func__,
(once_regs[ONCE_REG_IDX_OPABF11].reg >> 1),
once_regs[ONCE_REG_IDX_OPABDR].reg,
if (((chip>>5)&0x1f) == 0)
chip += 300;
- LOG_INFO("DSP56%03d device found", chip);
+ LOG_INFO("DSP56%03" PRId32 " device found", chip);
/* Clear all breakpoints */
dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
else
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_DEBUG("target->state: %s (%x)", target_state_name(target), once_status);
- LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
+ LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status);
+ LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
}
}
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
+ LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
return err;
}
return ERROR_OK;
}
-static int dsp563xx_soft_reset_halt(struct target *target)
-{
- LOG_DEBUG("%s", __func__);
- return ERROR_OK;
-}
-
static int dsp563xx_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
obcr_value |= OBCR_BP_MEM_P;
break;
default:
- LOG_ERROR("Unknown memType parameter (%d)", memType);
+ LOG_ERROR("Unknown memType parameter (%" PRIu32 ")", memType);
err = ERROR_TARGET_INVALID;
}
}
.poll = dsp563xx_poll,
.arch_state = dsp563xx_arch_state,
- .target_request_data = NULL,
-
.get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
.halt = dsp563xx_halt,
.assert_reset = dsp563xx_assert_reset,
.deassert_reset = dsp563xx_deassert_reset,
- .soft_reset_halt = dsp563xx_soft_reset_halt,
.read_memory = dsp563xx_read_memory_default,
.write_memory = dsp563xx_write_memory_default,