target_t -> struct target

[fw/openocd] / src / target / cortex_m3.h

diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index ba61b1cba45ab08f1f44e4b86dd25a1ccf93df2e..ed08323758d8ab279bd0de191f4cccc6ea94f16d 100644 (file)
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -29,9 +29,7 @@
 #include "register.h"
 #include "target.h"
 #include "armv7m.h"
-//#include "arm_adi_v5.h"
 
-extern char* cortex_m3_state_strings[];
 
 #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
 
@@ -47,6 +45,7 @@ extern char* cortex_m3_state_strings[];
 #define DCRSR_WnR      (1 << 16)
 
 #define DWT_CTRL       0xE0001000
+#define DWT_CYCCNT     0xE0001004
 #define DWT_COMP0      0xE0001020
 #define DWT_MASK0      0xE0001024
 #define DWT_FUNCTION0  0xE0001028
@@ -62,8 +61,6 @@ extern char* cortex_m3_state_strings[];
 #define FP_COMP6       0xE0002020
 #define FP_COMP7       0xE0002024
 
-#define DWT_CTRL       0xE0001000
-
 /* DCB_DHCSR bit and field definitions */
 #define DBGKEY         (0xA05F << 16)
 #define C_DEBUGEN      (1 << 0)
@@ -80,7 +77,12 @@ extern char* cortex_m3_state_strings[];
 /* DCB_DEMCR bit and field definitions */
 #define        TRCENA                  (1 << 24)
 #define        VC_HARDERR              (1 << 10)
+#define        VC_INTERR               (1 << 9)
 #define        VC_BUSERR               (1 << 8)
+#define        VC_STATERR              (1 << 7)
+#define        VC_CHKERR               (1 << 6)
+#define        VC_NOCPERR              (1 << 5)
+#define        VC_MMERR                (1 << 4)
 #define        VC_CORERESET    (1 << 0)
 
 #define NVIC_ICTR              0xE000E004
@@ -117,42 +119,27 @@ extern char* cortex_m3_state_strings[];
 #define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
 #define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 
-/* Use MRS/MSR to read/write any of these special registers.  Some of
- * them (xPSR, MSP, PSP) are always available using DCRxR.  Starting in
- * Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available
- * through DCRxR.
- * NOTE: this listing omits xPSR components and other mixtures.
- */
-#define SR_XPSR                3
-#define SR_MSP         8
-#define SR_PSP         9
-#define SR_PRIMASK     16
-#define SR_BASEPRI     17
-#define SR_BASEPRI_MAX 18
-#define SR_FAULTMASK   19
-#define SR_CONTROL     20
-
-typedef struct  cortex_m3_fp_comparator_s
+struct cortex_m3_fp_comparator
 {
        int used;
        int type;
        uint32_t fpcr_value;
        uint32_t fpcr_address;
-} cortex_m3_fp_comparator_t;
+};
 
-typedef struct  cortex_m3_dwt_comparator_s
+struct cortex_m3_dwt_comparator
 {
        int used;
        uint32_t comp;
        uint32_t mask;
        uint32_t function;
        uint32_t dwt_comparator_address;
-} cortex_m3_dwt_comparator_t;
+};
 
-typedef struct cortex_m3_common_s
+struct cortex_m3_common
 {
        int common_magic;
-       arm_jtag_t jtag_info;
+       struct arm_jtag jtag_info;
 
        /* Context information */
        uint32_t dcb_dhcsr;
@@ -165,45 +152,22 @@ typedef struct cortex_m3_common_s
        int fp_code_available;
        int fpb_enabled;
        int auto_bp_type;
-       cortex_m3_fp_comparator_t *fp_comparator_list;
+       struct cortex_m3_fp_comparator *fp_comparator_list;
 
        /* Data Watchpoint and Trace (DWT) */
        int dwt_num_comp;
        int dwt_comp_available;
-       cortex_m3_dwt_comparator_t *dwt_comparator_list;
-
-       /* Interrupts */
-       int intlinesnum;
-       uint32_t *intsetenable;
-
-       armv7m_common_t armv7m;
-//     swjdp_common_t swjdp_info;
-       void *arch_info;
-} cortex_m3_common_t;
-
-extern void cortex_m3_build_reg_cache(target_t *target);
+       struct cortex_m3_dwt_comparator *dwt_comparator_list;
+       struct reg_cache *dwt_cache;
 
-int cortex_m3_poll(target_t *target);
-int cortex_m3_halt(target_t *target);
-int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
+       struct armv7m_common armv7m;
+};
 
-int cortex_m3_assert_reset(target_t *target);
-int cortex_m3_deassert_reset(target_t *target);
-int cortex_m3_soft_reset_halt(struct target_s *target);
-
-int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-
-int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-
-//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
+static inline struct cortex_m3_common *
+target_to_cm3(struct target *target)
+{
+       return container_of(target->arch_info,
+                       struct cortex_m3_common, armv7m);
+}
 
 #endif /* CORTEX_M3_H */