#ifndef CORTEX_M3_H
#define CORTEX_M3_H
-#include "register.h"
-#include "target.h"
#include "armv7m.h"
-//#include "arm_adi_v5.h"
-extern char* cortex_m3_state_strings[];
#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
#define DCRSR_WnR (1 << 16)
#define DWT_CTRL 0xE0001000
+#define DWT_CYCCNT 0xE0001004
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
-#define DWT_CTRL 0xE0001000
-
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
-typedef struct cortex_m3_fp_comparator_s
+struct cortex_m3_fp_comparator
{
int used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
-} cortex_m3_fp_comparator_t;
+};
-typedef struct cortex_m3_dwt_comparator_s
+struct cortex_m3_dwt_comparator
{
int used;
uint32_t comp;
uint32_t mask;
uint32_t function;
uint32_t dwt_comparator_address;
-} cortex_m3_dwt_comparator_t;
+};
+
+enum cortex_m3_soft_reset_config
+{
+ CORTEX_M3_RESET_SYSRESETREQ,
+ CORTEX_M3_RESET_VECTRESET,
+};
+
+enum cortex_m3_isrmasking_mode
+{
+ CORTEX_M3_ISRMASK_AUTO,
+ CORTEX_M3_ISRMASK_OFF,
+ CORTEX_M3_ISRMASK_ON,
+};
-typedef struct cortex_m3_common_s
+struct cortex_m3_common
{
int common_magic;
- arm_jtag_t jtag_info;
+ struct arm_jtag jtag_info;
/* Context information */
uint32_t dcb_dhcsr;
int fp_code_available;
int fpb_enabled;
int auto_bp_type;
- cortex_m3_fp_comparator_t *fp_comparator_list;
+ struct cortex_m3_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
int dwt_num_comp;
int dwt_comp_available;
- cortex_m3_dwt_comparator_t *dwt_comparator_list;
+ struct cortex_m3_dwt_comparator *dwt_comparator_list;
+ struct reg_cache *dwt_cache;
- /* Interrupts */
- int intlinesnum;
- uint32_t *intsetenable;
+ enum cortex_m3_soft_reset_config soft_reset_config;
- armv7m_common_t armv7m;
-// swjdp_common_t swjdp_info;
- void *arch_info;
-} cortex_m3_common_t;
+ enum cortex_m3_isrmasking_mode isrmasking_mode;
-extern void cortex_m3_build_reg_cache(target_t *target);
+ struct armv7m_common armv7m;
+};
-int cortex_m3_poll(target_t *target);
-int cortex_m3_halt(target_t *target);
-int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
-
-int cortex_m3_assert_reset(target_t *target);
-int cortex_m3_deassert_reset(target_t *target);
-int cortex_m3_soft_reset_halt(struct target_s *target);
-
-int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-
-int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-
-//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
+static inline struct cortex_m3_common *
+target_to_cm3(struct target *target)
+{
+ return container_of(target->arch_info,
+ struct cortex_m3_common, armv7m);
+}
#endif /* CORTEX_M3_H */