#define DCRSR_WnR (1 << 16)
#define DWT_CTRL 0xE0001000
+#define DWT_CYCCNT 0xE0001004
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
-#define DWT_CTRL 0xE0001000
-
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
int dwt_num_comp;
int dwt_comp_available;
cortex_m3_dwt_comparator_t *dwt_comparator_list;
-
- /* Interrupts */
- int intlinesnum;
- uint32_t *intsetenable;
+ struct reg_cache_s *dwt_cache;
armv7m_common_t armv7m;
void *arch_info;
} cortex_m3_common_t;
+static inline struct cortex_m3_common_s *
+target_to_cm3(struct target_s *target)
+{
+ return container_of(target->arch_info,
+ struct cortex_m3_common_s, armv7m);
+}
+
#endif /* CORTEX_M3_H */